Computing apparatus

1. A reconfigurable computing apparatus comprising:

a plurality of computing element networks respectively formed of computing elements of an identical bit width, the bit width of each of the computing element networks differing according to computing element network;

a bit width converting element that converts bit widths between the computing element networks;

a control signal-dedicated network that is formed of computing elements, is reconfigurable, and controls each of the computing element networks; and

a sequencer that controls a timing at which circuit configurations are switched with respect to the computing element networks, the control signal-dedicated network, and the bit width converting element.

2. The reconfigurable computing apparatus according to claim 1 , wherein

the computing element network is separated into a network of register-less computing elements and a network of register-included computing elements, the network of register-less computing elements and the network of register-included computing elements being connected in series or as a loop.

3. The reconfigurable computing apparatus according to claim 2 , wherein

the network of register-less computing elements is connected to the network of register-included computing elements, and

the network of register-included computing elements is connected to the bit converting element.

4. The reconfigurable computing apparatus according to claim 3 , wherein the network of register-less computing elements includes computing elements without registers, a register file, and a first selector switch.

5. The reconfigurable computing apparatus according to claim 4 , wherein

the network of register-less computing elements is arranged in a matrix of m rows and n columns of the computing elements, among which a first column of the computing elements is connected to a first register file that is connected to the network of register-included computing elements and the n-th column of the computing elements is connected to a second register file that receives output from the n-th column of the computing elements,

the first selector switch switches connection relationships between output from a computing element and input to a computing element downstream, is sandwiched between the columns of the computing elements, and connected enabling bidirectional data transmission with the first register file and the second register file and data transmission to the first selector switch immediately downstream.

6. The reconfigurable computing apparatus according to claim 3 , wherein the network of register-included computing elements includes computing elements with registers and a second selector switch.

7. The reconfigurable computing apparatus according to claim 6 , wherein

the computing elements with registers are connected to the second selector switch enabling bidirectional data transmission with the second selector switch,

the second selector switch is connected with the network of computing elements without registers enabling bidirectional data transmission with the computing elements without registers.

8. The reconfigurable computing apparatus according to claim 4 , wherein the control signal-dedicated network, based on a control signal from a computing element network, controls the computing elements of the computing element network or the computing elements of another computing element network.

9. The reconfigurable computing apparatus according to claim 6 , wherein the control signal-dedicated network, based on a control signal from a computing element network, controls the computing elements of the computing element network or the computing elements of another computing element network.