Multiprocessor system configured as system LSI

1. A multiprocessor system configured as a system LSI, the multiprocessor system comprising:

a plurality of processor units each transmitting an interrupt request signal indicating an interrupt request for which an interrupt-request destination processor unit is specified and receiving an interrupt signal; and

an interrupt control circuit receiving the interrupt request signal from each of the plurality of processor units and transmitting the interrupt signal to each of the plurality of processor units,

wherein, in response to the interrupt request signal transmitted from each of the plurality of processor units, the interrupt control circuit transmits the interrupt signal to the interrupt-request destination processor unit specified by the interrupt request signal if the specified interrupt-request destination processor unit is not in a low power consumption state and transmits the interrupt signal to another processor unit different from the processor unit specified by the interrupt request signal if the specified interrupt-request destination processor unit is in the low power consumption state,

wherein the interrupt control circuit includes a function setting register indicating whether the change of the interrupt destination to each of the plurality of processor units is enabled or disabled, and

wherein the interrupt control circuit transmits the interrupt signal to the interrupt-request destination processor unit if the function setting register indicates that the change of the interrupt destination is disabled even when the interrupt-request destination processor unit specified by the interrupt request signal is in the low power consumption state.

2. The multiprocessor system configured as a system LSI according to claim 1 ,

wherein the other processor unit is not in the low power consumption state.

3. The multiprocessor system configured as a system LSI according to claim 2 ,

wherein, if all the processor units are in the low power consumption state, the interrupt signal is transmitted to the interrupt-request destination processor unit.

4. The multiprocessor system configured as a system LSI according to claim 1 , further comprising:

an interrupt-destination priority order table in which an interrupt priority order of each processor unit is specified,

wherein the priority order in the interrupt-destination priority order table is set in the ascending order of a power consumption of each processor unit.

5. A multiprocessor system comprising:

a plurality of processor units transmitting an interrupt request signal and receiving an interrupt signal;

an interrupt control circuit receiving the interrupt request signal from one of the plurality of processor units and transmitting the interrupt signal to one of the plurality of processor units; and

an interrupt destination priority order table in which an interrupt priority order of the plurality of processor units is specified,

wherein the interrupt control circuit further includes a function setting register indicating whether the change of the interrupt destination to one of the plurality of processor units is enabled or disabled,

wherein, in response to the interrupt request signal transmitted from one of the plurality of processor units, the interrupt control circuit selects one of the plurality of processor units according to the interrupt priority order if the function setting register indicates that the change of the interrupt destination is disabled and transmits the interrupt signal to the detected processor unit.