Memory access control circuit and image processing system
View Patent ↗A memory access control circuit includes a first internal register, an address transmitting unit that sets a state of the first internal register to a first state to transmit a first address and sets a state of the first internal register to a second state to transmit a second address, a second internal register, a data receiving unit that sets a state of the second internal register to a third state to receive first data corresponding to the first address, performs data processing on the first data without delay, sets a state of the second internal register to a fourth state to receive second data corresponding to the second address, and performs data processing on the second data after delaying the second data by a given delay time, a first backup unit and a second backup unit.
1. A memory access control circuit, comprising:
a first internal register;
an address transmitting unit that transmits a first address obtained based on a first value which is set in the first internal register based on a first state signal indicating a first state and transmits a second address obtained based on a second value which is set in the first internal register based on the first state signal indicating a second state;
a second internal register;
a data receiving unit that receives first data corresponding to the first address, performs data processing on the first data without delay using a third value which is set in the second internal register based on a second state signal indicating a third state, receives second data corresponding to the second address, and performs data processing on the second data after delaying the second data by a given delay time using a fourth value which is set in the second internal register based on the second state signal indicating a fourth state;
a first backup unit; and
a second backup unit,
wherein, in response to completion of transmission of the first address from the address transmitting unit or the second address from the address transmitting unit, the first value or the second value in the first internal register is stored in the first backup unit, respectively, and
wherein, in response to completion of the data processing of the first data by the data receiving unit, the third value in the second internal register is stored in the second backup unit by utilizing the given delay time and the fourth value is set to the second internal register by the second backup unit.
2. The memory access control circuit according to claim 1 , further comprising:
a delay circuit that receives an end signal from the address transmitting unit and delays the end signal to generate the delayed end signal, the end signal indicating the completion of the transmission of the first address from the address transmitting unit,
wherein the data receiving unit delays the received series of second data by the given delay time in response to the delayed end signal delayed.
3. The memory access control circuit according to claim 1 , wherein the data processing includes storing the first data and the second data in a memory.
4. The memory access control circuit according to claim 2 , wherein the data processing includes storing the first data and the second data in a memory.
5. The memory access control circuit according to claim 2 , wherein the delay circuit includes FIFO.
6. The memory access control circuit according to claim 2 , wherein the data receiving unit includes:
a selector;
a first data path through which at least one of the first data and the second data is supplied to the selector without delay; and
a second data path through which at least one of the first data and the second data is supplied to the selector by delaying the at least one of the first data and the second data by a given delay time,
wherein the selector selects data of the first data path before arriving the delayed end signal, and selects data of the second data path after arriving the delayed end signal.
7. The memory access control circuit according to claim 2 , wherein the data receiving unit includes:
a plurality of flip flops coupled in series;
a shift register that sequentially delays at least one of the first data and the second data using the flip flops;
a selector that receives output data from the plurality of flip flops; and
a counter that starts counting in response to the delayed end signal,
wherein the selector selects one of output data from the plurality of flip flops according to a counter value.
8. The memory access control circuit according to claim 1 , further comprising:
a first control unit that controls a transition of the first state signal; and
a second control unit that controls a transition of the second state signal,
wherein the first control unit and the second control unit are separately provided.
9. The memory access control circuit according to claim 8 , wherein the first state signal and the second state signal four states, and
wherein the four states include a state in which a read address of first image data is transmitted, a state in which a read address of second image data is transmitted, a state in which a read address of third image data is transmitted, and a state in which a write address of fourth image data generated based on the first to third image data is transmitted.
10. The memory access control circuit according to claim 9 , wherein the first image data includes input image data,
wherein the second image data includes output image data,
wherein the third image data includes an alpha map, and
wherein the fourth image data includes output image data generated by alpha-blending of the input image data and the output image data using the alpha map.
11. An image processing system comprising:
a memory access control circuit that reads image data from an external memory; and
an image processing unit that processes the image data read by the memory access control circuit,
wherein the memory access control circuit includes:
a first internal register;
an address transmitting unit that transmits a first address obtained based on a first value which is set in the first internal register based on a first state signal indicating a first state and transmits a second address obtained based on a second value which is set in the first internal register based on the first state signal indicating a second state;
a second internal register;
a data receiving unit that receives first data corresponding to the first address, performs data processing on the first data without delay using a third value which is set in the second internal register based on a second state signal indicating a third state, receives second data corresponding to the second address, and performs data processing on the second data after delaying the second data by a given delay time using a fourth value which is set in the second internal register based on the second state signal indicating a fourth state;
a first backup unit; and
a second backup unit,
wherein, in response to completion of transmission of the first address from the address transmitting unit or the second address from the address transmitting unit, the first value or the second value in the first internal register is stored in the first backup unit, respectively, and
wherein, in response to completion of the data processing of the first data by the data receiving unit, the third value in the second internal register is stored in the second backup unit by utilizing the given delay time and the fourth value is set to the second internal register by the second backup unit.
12. The image processing system according to claim 11 , further comprising:
a delay circuit that receives an end signal from the address transmitting unit and delays the end signal to generate the delayed end signal, the end signal indicating the completion of the transmission of the first address from the address transmitting unit,
wherein the data receiving unit delays the received series of second data by the given delay time in response to the delayed end signal delayed.
13. The image processing system according to claim 11 , wherein the data processing includes storing the first data and the second data in a memory.
14. The image processing system according to claim 12 , wherein the data processing includes storing the first data and the second data in a memory.
15. The image processing system according to claim 12 , wherein the delay circuit includes FIFO.
16. The image processing system according to claim 12 , wherein the data receiving unit includes:
a selector;
a first data path through which at least one of the first data and the second data is supplied to the selector without delay; and
a second data path through which at least one of the first data and the second data is supplied to the selector by delaying the at least one of the first data and the second data by a given delay time,
wherein the selector selects data of the first data path before arriving the delayed end signal, and selects data of the second data path after arriving the delayed end signal.
17. The image processing system according to claim 12 , wherein the data receiving unit includes:
a plurality of flip flops coupled in series;
a shift register that sequentially delays at least one of the first data and the second data using the flip flops;
a selector that receives output data from the plurality of flip flops; and
a counter that starts counting in response to the delayed end signal,
wherein the selector selects one of output data from the plurality of flip flops according to a counter value.
18. The image processing system according to claim 11 , further comprising:
a first control unit that controls a transition of the first state signal; and
a second control unit that controls a transition of the second state signal,
wherein the first control unit and the second control unit are separately provided.
19. The image processing system according to claim 18 , wherein the first state signal and the second state signal indicate four states, and
wherein the four states include a state in which a read address of first image data is transmitted, a state in which a read address of second image data is transmitted, a state in which a read address of third image data is transmitted, and a state in which a write address of fourth image data generated based on the first to third image data is transmitted.
20. The image processing system according to claim 19 , wherein the first image data includes input image data,
wherein the second image data includes output image data,
wherein the third image data includes an alpha map, and
wherein the fourth image data includes output image data generated by alpha-blending of the input image data and the output image data using the alpha map.