Layout design method and semiconductor integrated circuit

1. A method of layout-designing a circuit based on circuit information by a computer, comprising:

generating layout information including a core region based on the circuit information;

laying out an I/O circuit in a region other than the core region of the layout information indicated by the circuit information;

determining a layout-permitted region of pads included in regions other than the core region and a layout region of said I/O circuit based on the circuit information; and

laying out the pads in the layout-permitted region, and

wherein the layout-permitted region is determined based on a needle length specified to probe in a semiconductor testing apparatus.

2. The method according to claim 1 , wherein the layout-permitted region is determined based on a wire length specified for wire bonding.

3. The method according to claim 2 , comprising:

comparing the needle length with the wire length, and

wherein the layout-permitted region is determined based on a comparison result.

4. A method of layout-designing a circuit based on circuit information by a computer, comprising:

generating layout information including a core region based on the circuit information;

laying out an I/O circuit in a region other than the core region of the layout information indicated by the circuit information;

determining a layout-permitted region of pads included in regions other than the core region and a layout region of said I/O circuit, based on the circuit information;

laying out the pads in the layout-permitted region;

acquiring a number of the pads and a pad area of each of the pads;

calculating an area of the layout-permitted region and a total area of the pads based on the number of the pads and the area of the pads;

comparing the area of the layout-permitted region with the total area and deciding whether the pads are laid out in the layout-permitted region; and

laying out the pads in the layout-permitted region based on a result of the deciding.

5. The method according to claim 4 , comprising:

expanding the layout-permitted region when the area of the layout-permitted region is smaller than the total area; and

comparing the area of an expanded layout-permitted region with the total area to decide whether the pads are laid out in the expanded layout-permitted region.

6. The method according to claim 4 , wherein the pads are laid out in the layout-permitted region when the area of the layout-permitted region is larger than the total area.

7. The method according to claim 1 , wherein a pad area is changed to a maximum area where a total area does not exceed an area of the layout-permitted region, and the changed pads are laid out.

8. The method according to claim 1 , wherein pads of a same type are laid out adjacent to one another.

9. A method of layout-designing a circuit based on circuit information by a computer, comprising:

generating layout information including a core region based on the circuit information;

laying out an I/O circuit in a region other than the core region of the layout information indicated by the circuit information;

determining a layout-permitted region of pads included in regions other than the core region and a layout region of said I/O circuit based on the circuit information; and

laying out the pads in the layout-permitted region, and

wherein the layout-permitted region is determined based on a wire length specified for wire bonding which is obtained from a constraint table.

10. The method according to claim 1 , comprising deciding whether a required number of the pads is laid out in the layout-permitted region.

11. The method according to claim 10 , comprising expanding the layout-permitted region, using a processor, when the layout-permitted region is smaller than a total area of a the required number of the pads.

12. The method according to claim 1 , wherein the layout-permitted region is divided into zones, and the laying out of the pads uses the zones to determine a layout position of each of the pads.

13. The method according to claim 1 , wherein the layout information includes a monitor region including only a transistor to measure information of said I/O circuit.

14. The method according to claim 9 , wherein a pad pitch is read from the constraint table and the laying out is accomplished so that the pads align at an equal space larger than the pad pitch.

15. The method according to claim 9 , wherein the constraint table is read from a memory of the computer or an external device.