System LSI having plural buses
View Patent ↗A system LSI includes first and second memories, first and second buses, a bus bridge that performs signal transfer between the first and second buses, a first bus system connecting to the first bus and accessing the first or second memory, a second bus system connecting to the second bus and accessing the first or second memory, a memory access circuit having first and second bus-side input/output terminals that perform signal transfer to/from the first and second buses and first and second memory-side input/output terminals that perform signal transfer to/from the first and second memories.
1. A system LSI comprising:
first and second memories;
first and second buses;
a bus bridge that performs signal transfer between the first and second buses;
a memory access circuit having first and second bus-side input/output terminals that perform signal transfer to/from the first and second buses, first and second memory-side input/output terminals that perform signal transfer to/from the first and second memories,
a first access path that connects the first bus-side input/output terminal and the first memory-side input/output terminal,
a second access path that connects the second bus-side input/output terminal and the second memory-side input/output terminal,
a third access path that connects the first bus-side input/output terminal and the second memory-side input/output terminal,
a fourth access path that connects the second bus-side input/output terminal and the first memory-side input/output terminal,
an address region managing portion that receives an access destination address in the first or second memory, which is output by the first or second bus; and outputs a signal that designates the first or second memory address in accordance with a path-selection-mode setting signal to the first or second memory-side input/output terminal, wherein
the memory access circuit
performs signal transfer through the first to fourth access paths; and
for memory access by the first or second bus, selects at least one of the first to fourth access paths in accordance with a path-selection-mode setting signal from the first or second bus, wherein the first or second bus has an access destination address space including a first address space in the first memory and a second address space, which is continuous to the first address space, in the second memory; and if the path-selection-mode setting signal indicates a one-all mode, the address region managing portion identifies either first or second memory to access on the basis of the access destination address space, converts the access destination address to an address in the first or second address space and outputs the result, and the memory access circuit selects one of the first to fourth access paths in accordance with the identification result by the address region managing portion.
2. The system LSI according to claim 1 ,
the memory access circuit having an arbitrating portion, wherein:
the arbitrating portion
receives busy signals indicating memory access by the first or second bus; and
when receiving an access request signal from the first or second bus to the first or second memory,
in accordance with the path-selection-mode setting signal,
permits accessing memory without reference to the busy signals; or
refers to the busy signals and inhibits accessing memory if at least one memory is being accessed or permits accessing memory if both of the memories are not being accessed.
3. The system LSI according to claim 1 , wherein:
the memory access circuit
selects the first and second access paths if the path-selection-mode setting signal indicates a separate mode; or
selects the third and fourth access paths if the path-selection-mode setting signal indicates a cross mode.
4. The system LSI according to claim 3 ,
wherein:
the address region managing portion outputs the access destination address without performing address conversion thereon if the path-selection-mode setting signal indicates the separate mode or the cross mode.
5. The system LSI according to claim 1 , wherein:
the memory access circuit
selects the first to the fourth access paths if the path-selection-mode setting signal indicates a mirror mode.
6. The system LSI according to claim 5 ,
wherein:
an address region managing portion outputs the access destination address without performing address conversion thereon if the path-selection-mode setting signal indicates the mirror mode.
7. The system LSI according to claim 1 , wherein:
the memory access circuit selects the first and third access paths or the second and fourth access paths if the path-selection-mode setting signal indicates a mirror mode.
8. The system LSI according to claim 1 ,
the memory access circuit having an arbitrating portion, wherein:
the arbitrating portion receives busy signals indicating memory access by the first or second bus; and when receiving an access request signal from the first or second bus to the first or second memory, if the path-selection-mode setting signal indicates a separate mode in which the first and second access paths are selected or a cross mode in which the third and fourth access paths are selected, permits accessing memory without reference to the busy signals, or if the path-selection-mode setting signal indicates a mirror mode in which the first to fourth access paths are selected or a one-all mode in which one of the first to fourth access paths is selected, refers to the busy signals and inhibits accessing memory if at least one memory is being accessed and permits the access if both of the memories are not being accessed.
9. The system LSI according to claim 1 , wherein the first and second buses connect to data processing circuits that perform data processing, and the first and second bus perform processing by reading signals simultaneously from one of the first and second memory and the other, respectively.
10. The system LSI according to claim 1 , wherein the memory access circuit has two or more path modes, the path mode includes a separate mode in which the first and second access paths are selected, a cross mode in which the third and fourth access paths are selected, a mirror mode in which the first to fourth access paths are selected, and a one-all mode in which one of the first to fourth access paths is selected and the memory access circuit selects an access path in accordance with the path-selection-mode setting signal.
11. The system LSI according to claim 10 , wherein in the one-all mode, the first and second bus have an access destination address space including a first address space in the first memory and a second address space, which is continuous to the first address space, in the second memory; and the address region managing portion identifies either first or second memory to access on the basis of the access destination address space, converts the access destination address to an address in the first or second address space and outputs the result, and the memory access circuit selects one of the first to fourth access paths in accordance with the identification result by the address region managing portion.
12. A system LSI having first and second memories, the system comprising:
a plurality of buses;
a memory access circuit having first and second bus-side input/output terminals that perform signal transfer to/from one of the plurality of buses, first and second memory-side input/output terminals that perform signal transfer to/from the first and second memories,
a first access path that connects the first bus-side input/output terminal and the first memory-side input/output terminal,
a second access path that connects the second bus-side input/output terminal and the second memory-side input/output terminal,
a third access path that connects the first bus-side input/output terminal and the second memory-side input/output terminal,
a fourth access path that connects the second bus-side input/output terminal and the first memory-side input/output terminal,
an address region managing portion that receives an access destination address in the first or second memory, which is output by one of the plurality of buses; and outputs a signal that designates the first or second memory address in accordance with a path-selection-mode setting signal to the first or second memory-side input/output terminal, wherein
the memory access circuit performs signal transfer through the first to fourth access path; and
for memory access by one of the plurality of buses, selects at least one of the first to fourth access paths in accordance with a path-selection-mode setting signal from one of the plurality of buses, wherein the plurality of buses have an access destination address space including a first address space in the first memory and a second address space, which is continuous to the first address space, in the second memory; and
if the path-selection-mode setting signal indicates a one-all mode, the address region managing portion identifies either first or second memory to access on the basis of the access destination address space, converts the access destination address to an address in the first or second address space and outputs the result, and the memory access circuit selects one of the first to fourth access paths in accordance with the identification result by the address region managing portion.
13. The system LSI according to claim 12 , wherein:
the memory access circuit selects the first to the fourth access paths if the path-selection-mode setting signal indicates a mirror mode.
14. The system LSI according to claim 13 ,
wherein the address region managing portion outputs the access destination address without address conversion thereon if the path-selection-mode setting signal indicates the mirror mode.
15. The system LSI according to claim 12 , wherein:
the memory access circuit selects the first and third access paths or the second and fourth access paths if the path-selection-mode setting signal indicates a mirror mode.