Deposited semiconductor structure to minimize N-type dopant diffusion and method of making

1. A microelectronic structure comprising a layerstack, the layerstack comprising:

a first layer comprising semiconductor material that is very heavily n-doped before being annealed, having a first-layer before-anneal dopant concentration, wherein the first layer is above a substrate, and wherein the first layer is heavily n-doped after being annealed, having a first-layer after-anneal dopant concentration, the first-layer before-anneal dopant concentration exceeding the first-layer after-anneal concentration;

a second layer comprising semiconductor material that is not heavily doped before being annealed, having a second-layer before-anneal dopant concentration, the second layer being about as thick as the first layer, wherein the second layer is above and in contact with the first layer, and wherein the second layer comprises heavily n-doped semiconductor material after being annealed, having a second-layer after-anneal dopant concentration, the second-layer after-anneal dopant concentration exceeding the second-layer before-anneal concentration;

a third layer comprising semiconductor material that is above and in contact with the second layer and that is not heavily n-doped before or after being annealed, the third layer having a third-layer dopant concentration; and

a fourth layer comprising a semiconductor material that is above and in contact with the third layer;

wherein:

the first, second, and third layers are portions of a vertically oriented junction diode;

the diode is a p-i-n diode, the third layer is undoped or lightly doped, and the third layer comprises germanium; and

the fourth layer comprises silicon, the fourth layer is heavily p-doped, and the fourth layer is a portion of the vertically oriented junction diode.

2. The microelectronic structure of claim 1 , wherein the diode is vertically disposed between a bottom conductor and a top conductor, wherein a nonvolatile memory cell comprises a portion of the bottom conductor, the diode, and a portion of the top conductor.

3. The microelectronic structure of claim 2 , wherein the first, second, third and fourth layers have been patterned and etched to form a pillar.

4. The microelectronic structure of claim 2 , wherein the non-volatile memory cell resides in a monolithic three dimensional memory array comprising:

a) a first memory level formed above the substrate, the first memory level comprising:

i) a plurality of the bottom conductors, the bottom conductors being substantially parallel and substantially coplanar;

ii) a plurality of the top conductors, the top conductors being substantially parallel and substantially coplanar; and

iii) a plurality of the non-volatile memory cells; and

b) at least a second memory level monolithically formed above the first memory level.

5. The microelectronic structure of claim 2 , wherein the memory cell further comprises a reversible state-change element, the reversible state-change element disposed between the diode and the bottom conductor or between the diode and the top conductor.

6. The microelectronic structure of claim 5 , wherein the reversible state-change element comprises a layer of a resistivity-switching metal oxide or nitride compound selected from the group consisting of NiO, Nb 2 O 5 , TiO 2 , HfO 2 , Al 2 O 3 , CoO, MgO x , CrO 2 , VO, BN, and AIN.