Process for manufacturing semiconductor integrated circuit device
View Patent ↗In order to provide an anticorrosive technique for metal wirings formed by a chemical mechanical polishing (CMP) method, a process for manufacturing a semiconductor integrated circuit device according to the invention comprises the steps of: forming a metal layer of Cu (or a Cu alloy containing Cu as a main component) over the major face of a wafer and then planarizing the metal layer by a chemical mechanical polishing (CMP) method to form metal wirings; anticorroding the planarized major face of the wafer to form a hydrophobic protective film over the surfaces of the metal wirings; immersing the anticorroded major face of the wafer or keeping the same in a wet state so that it may not become dry; and post-cleaning the major face, kept in the wet state, of the wafer.
1. A process for manufacturing a semiconductor integrated circuit device, comprising:
(a) forming an insulating film over a first major surface of a wafer;
(b) forming a wiring groove in the insulating film by patterning the insulating film;
(c) forming a metal layer including copper as its principal component, over the insulating film and in the wiring groove;
(d) removing the metal layer outside the wiring groove by a chemical mechanical polishing method using a polishing slurry, so as to leave the metal layer in the wiring groove, said removing being performed in a wafer processing apparatus;
(e) performing a pre-cleaning treatment to the first major surface of the wafer with pure water in order to remove the polishing slurry;
(f) after (e), making the first major surface of the wafer wet by a wet treatment and transferring the wafer to a post cleaning section through a light shielding structure in the wafer processing apparatus;
(g) after (f), performing a post cleaning treatment to the first major surface of the wafer with a liquid chemical or pure water in the post cleaning section; and
(h) making the first major surface of the wafer dry,
wherein (d) to (h) are performed in the wafer processing apparatus which processes by a single wafer processing method.
2. A process for manufacturing a semiconductor integrated circuit device according to claim 1 , wherein the metal layer left in the wiring groove in (d) is a metal wiring of a damascene or dual damascene wiring.
3. A process for manufacturing a semiconductor integrated circuit device according to claim 1 , wherein the wet treatment in (f) is performed by a water shower at a wet treatment section disposed on the way of transferring in (f).
4. A process for manufacturing a semiconductor integrated circuit device according to claim 1 , wherein the post cleaning treatment is performed by scrub or brush cleaning.
5. A process for manufacturing a semiconductor integrated circuit device according to claim 1 , wherein the light shielding structure keeps an illuminance of the inside thereof 100 lux or less.
6. A process for manufacturing a semiconductor integrated circuit device according to claim 1 , wherein the post cleaning section has a light shielding structure keeping an illuminance of the inside of the post cleaning section 100 lux or less.
7. A process for manufacturing a semiconductor integrated circuit device according to claim 6 , wherein (h) is performed in the post cleaning section.
8. A process for manufacturing a semiconductor integrated circuit device according to claim 1 , wherein the wet treatment in (f) is performed by pure water at a wet treatment section disposed on the way of transferring in (f).
9. A process for manufacturing a semiconductor integrated circuit device, comprising:
(a) forming an insulating film over a first major surface of a wafer;
(b) forming a wiring groove in the insulating film by patterning the insulating film;
(c) forming a metal layer including copper as its principal component, over the insulating film and in the wiring groove;
(d) removing the metal layer outside the wiring groove by a chemical mechanical polishing method using a polishing slurry, so as to leave the metal layer in the wiring groove;
(e) performing a pre-cleaning treatment to the first major surface of the wafer with pure water in order to remove the polishing slurry;
(f) after (e), transferring the wafer to a post cleaning section;
(g) after (f), performing scrub or brush cleaning to the first major surface of the wafer with a liquid chemical or pure water in the post cleaning section; and
(h) making the first major surface of the wafer dry,
wherein (d) to (h) are performed in a wafer processing apparatus which has light shielding structure, and
wherein (f) includes:
(i) performing a wet treatment to the first major surface of the wafer by pure water.
10. A process for manufacturing a semiconductor integrated circuit device according to claim 9 , wherein the metal layer left in the wiring groove in (d) is a metal wiring of a damascene or dual damascene wiring.
11. A process for manufacturing a semiconductor integrated circuit device according to claim 9 , wherein the light shielding structure keeps an illuminance of the inside thereof 100 lux or less.
12. A process for manufacturing a semiconductor integrated circuit device according to claim 9 , wherein (e) is performed prior to a substantial progress of corrosion of the metal layer left in the wiring groove.
13. A process for manufacturing a semiconductor integrated circuit device according to claim 9 , wherein the first major surface of the wafer is kept wet from the end of (d) to the end of (g).
14. A process for manufacturing a semiconductor integrated circuit device according to claim 9 , wherein an anti-corrosion treatment is applied to the metal layer between (e) and (f).
15. A process for manufacturing a semiconductor integrated circuit device according to claim 9 , wherein the wet treatment in (i) is performed by a water shower.