Lookup table, semiconductor integrated circuit, method for making lookup table and method for making semiconductor integrated circuit
View Patent ↗A lookup table includes a single via layer having 2 N via insertion portions corresponding to 2 N input patterns provided from N input terminals; and a via inserted into at least one of the via insertion portions, the via connecting the input terminal and an output terminal.
1. A lookup table, comprising:
M input terminals, each provided with an input pattern, where M is at least one;
an output terminal connected to an output node;
a selection circuit including a number N of NMOS transistors that are arranged in series between the output node and a ground terminal, wherein a gate of each NMOS transistor is connected to one of the M input terminals, the output node is connected to a drain of one of the N NMOS transistors, and N is at least one; and
a conductive metal which connects to the output node and the drain of one of the N NMOS transistors, and
wherein the selection circuit determines the number of NMOS transistors required to generate an output based on positioning of vias inserted among the M input terminals.
2. The lookup table according to claim 1 , wherein the selection circuit is formed by M×2 M transistors whose on/off states are determined on the basis of the input patterns.
3. The lookup table according to claim 1 , wherein the selection circuit is formed by a plurality of transistors whose on/off states are determined on the basis of the input patterns, the number of the transistors being given by a following equation:
∑
i
=
1
M
2
i
≤
n
≤
M
×
2
M
where n is the number of the transistors.
4. The lookup table according to claim 1 , wherein the number of NMOS transistors required to generate the output is determined by analyzing locations of via insertions within a layer in relation to an input of each of the M input terminals.
5. A semiconductor integrated circuit, comprising:
a lookup table including
M input terminals, each provided with an input pattern, where M is at least one;
an output terminal connected to a first output node;
a selection circuit including a number N of NMOS transistors that are arranged in series between the first output node and a ground terminal, wherein a gate of each NMOS transistor is connected to one of the input terminals, the first output node is connected to a drain of one of the N NMOS transistors, and N is at least one; and
a conductive metal which connects to the output node and the drain of one of the N NMOS transistors;
a group of circuit elements provided outside the lookup table; and
a second output node interconnecting the circuit elements in the group of circuit elements, and connecting the circuit elements and the output terminal of the lookup table, and
wherein the selection circuit determines the number of NMOS transistors required to generate an output based on positioning of vias inserted among the M input terminals.
6. The semiconductor integrated circuit according to claim 5 , wherein the number of NMOS transistors required to generate the output is determined by evaluating locations of via insertions within a layer in relation to an input of each of the M input terminals.
7. A semiconductor integrated circuit, comprising:
a plurality of first semiconductor integrated circuits;
a third output node connecting a wiring member from the plural first semiconductor integrated circuits, and interconnecting the first semiconductor integrated circuits, wherein each of the first semiconductor integrated circuits, includes:
a lookup table including M of input terminals, each provided with an input pattern, where M is at least one;
an output terminal connected to a first output node;
a selection circuit including a number N of NMOS transistors that are arranged in series between the first output node and a ground terminal, wherein a gate of each NMOS transistor is connected to one of the input terminals, and the first output node is connected to a drain of one of the N NMOS transistors, and N is at least one; and
a conductive metal which connects to the output node and the drain of one of the N NMOS transistors;
a group of circuit elements provided outside the lookup table; and
a second output node interconnecting the circuit elements in the group of circuit elements and connecting the circuit elements and the output terminal of the lookup table, and
wherein the selection circuit determines the number of NMOS transistors required to generate an output based on positioning of vias inserted among the M input terminals.
8. The semiconductor integrated circuit according to claim 7 , wherein the number of NMOS transistors required to generate the output is determined based on locations of via insertions within a layer in relation to an input of each of the M input terminals.