Stacked chip assembly having vertical vias

1. A method of forming a stacked microelectronic assembly comprising the steps of:

(a) stacking a first semiconductor element atop a second semiconductor element, each of the first and second semiconductor elements having a front surface, a rear surface remote from the front surface, and a conductive pad exposed at the front surface, a first opening extending from the rear surface towards the front surface, and a second opening extending from the first opening at least to the respective conductive pad, the first and second openings having respective interior surfaces extending at nonzero angles relative to each other, wherein at least the second opening of the first semiconductor element extends through the conductive pad of the first semiconductor element, and the conductive pad of the first semiconductor element overlies the conductive pad of the second semiconductor element; and then

(b) depositing an electrically conductive material onto a surface below and through the conductive pad of the second semiconductor element and within the first and second openings of each semiconductor element to form an electrically conductive element extending through the first and second openings of each of the first and second semiconductor elements, the conductive element conforming to contours of the interior surfaces of the first and second openings and electrically connecting the conductive pads.

2. The method of claim 1 , wherein each of the conductive pads of the first and second semiconductor elements has a bottom surface adjacent the second opening of the respective semiconductor element, and the conductive element contacts the bottom surface of each of the respective conductive pads.

3. The method of claim 1 , wherein the conductive pad of at least the first semiconductor element has an inner surface exposed within the second opening, the inner surface extending from a bottom surface of the conductive pad adjacent the second opening to a top surface thereof remote from the bottom surface, wherein the conductive element contacts the inner surface of the conductive pad of at least the first semiconductor element.

4. The method of claim 1 , wherein a dielectric material at least partly overlies the interior surfaces of the first and second openings of each of the first and second semiconductor elements.

5. The method of claim 4 , wherein the dielectric material is a polymeric material.

6. The method of claim 4 , wherein step (b) includes removing a portion of the dielectric material by a method including at least one of: mechanical milling, sandblasting, or directing a laser toward at least a portion of the interior surfaces of the first and second openings to ablate a portion of the dielectric material and a portion of a sacrificial layer.

7. The method of claim 1 , wherein step (b) includes filling the first and second openings of each of the first and second semiconductor elements with the electrically conductive element.

8. The method of claim 1 , wherein step (b) includes forming a metal layer lining the first and second openings of the second semiconductor element, and forming a dielectric layer overlying the metal layer within the first and second openings, the metal layer extending at least partially through the conductive pad of the second semiconductor element.

9. The method of claim 8 , wherein the metal layer extends through the entire thickness of the conductive pad of the second semiconductor element.

10. The method of claim 1 , wherein at least the first semiconductor element has a plurality of active semiconductor devices disposed therein.

11. The method of claim 10 , wherein the second semiconductor element has a plurality of active semiconductor devices disposed therein.

12. A method of forming a stacked microelectronic assembly comprising the steps of:

(a) stacking a first semiconductor element atop a second semiconductor element, each of the first and second semiconductor elements having a front surface, a rear surface remote from the front surface, and a conductive pad exposed at the front surface and separated from a semiconductor layer of the semiconductor element by a dielectric layer, a first opening extending from the rear surface towards the front surface, and a second opening extending from the first opening and exposing a portion of the dielectric layer adjacent to the respective conductive pad, the first and second openings having respective interior surfaces extending at angles relative to each other, and a dielectric region at least substantially filling the first and second openings, wherein the conductive pad of the first semiconductor element overlies the conductive pad of the second semiconductor element;

(b) forming a third opening extending through the dielectric region within the first and second openings and extending through the conductive pad of at least the first semiconductor element; and

(c) forming an electrically conductive element extending through the third opening, the conductive element electrically connecting the conductive pads.

13. The method of claim 12 , wherein the conductive pad of at least the first semiconductor element has an inner surface exposed within the second opening, the inner surface extending from a bottom surface of the conductive pad adjacent the second opening to a top surface thereof remote from the bottom surface, the conductive element contacting the inner surface of the conductive pad of at least the first semiconductor element.

14. The method of claim 12 , wherein at least a portion of the conductive element does not conform to a contour of the respective interior surfaces of the first and second openings in the respective first and second semiconductor elements.

15. The method of claim 12 , wherein the dielectric region is a polymeric material.

16. The method of claim 12 , wherein step (b) includes removing a portion of the dielectric region by a method including at least one of: mechanical milling, sandblasting, or directing a laser toward at least a portion of the interior surfaces of the first and second openings to ablate a portion of the dielectric region and a portion of a sacrificial layer.

17. The method of claim 12 , wherein step (c) includes filling the third opening with the electrically conductive element.

18. The method of claim 12 , wherein step (c) includes forming a metal layer lining the third opening, and forming a dielectric layer overlying the metal layer within the third opening, the metal layer extending at least partially through the conductive pad of the second semiconductor element.

19. The method of claim 18 , wherein the metal layer extends through the entire thickness of the conductive pad of the second semiconductor element.

20. The method of claim 12 , wherein at least the first semiconductor element has a plurality of active semiconductor devices disposed therein.

21. The method of claim 20 , wherein the second semiconductor element has a plurality of active semiconductor devices disposed therein.

22. A method of forming a stacked microelectronic assembly comprising the steps of:

(a) stacking a first semiconductor element atop a second semiconductor element, each of the first and second semiconductor elements having a front surface, a rear surface remote from the front surface, and a conductive pad exposed at the front surface and separated from a semiconductor layer of the semiconductor element by a dielectric layer, a first opening extending from the rear surface towards the front surface, and a second opening extending from the first opening and exposing a portion of the dielectric layer adjacent to the respective conductive pad, the first and second openings having respective interior surfaces extending at angles relative to each other, wherein at least the second opening of the first semiconductor element extends through the conductive pad of the first semiconductor element, and the conductive pad of the first semiconductor element overlies the conductive pad of the second semiconductor element; and

(b) forming an electrically conductive element extending through the first and second openings of each of the first and second semiconductor elements, the conductive element conforming to contours of the interior surfaces of the first and second openings and electrically connecting the conductive pads.

23. An assembly comprising:

a first semiconductor element stacked atop a second semiconductor element, each of the first and second semiconductor elements having a front surface, a rear surface remote from the front surface, and a conductive pad exposed at the front surface, a first opening extending from the rear surface towards the front surface, and a second opening extending from the first opening at least to the respective conductive pad, the first and second openings having respective interior surfaces extending at nonzero angles relative to each other, wherein at least the second opening of the first semiconductor element extends through the conductive pad of the first semiconductor element, and the conductive pad of the first semiconductor element overlies the conductive pad of the second semiconductor element; and

a monolithic electrically conductive element extending through the first and second openings of each of the first and second semiconductor elements, the conductive element conforming to contours of the interior surfaces of the first and second openings and electrically connecting the conductive pads.

24. The assembly of claim 23 , wherein each of the conductive pads of the first and second semiconductor elements has a bottom surface adjacent the second opening of the respective semiconductor element, and each of the conductive element contacts the bottom surface of the respective conductive pad.

25. The assembly of claim 23 , wherein the conductive pad of at least the first semiconductor element has an inner surface exposed within the second opening, the inner surface extending from a bottom surface of the conductive pad adjacent the second opening to a top surface thereof remote from the bottom surface, wherein the conductive element contacts the inner surface of the conductive pad of at least the first semiconductor element.

26. The assembly of claim 23 , wherein a dielectric material at least partly overlies the interior surfaces of the first and second openings of each of the first and second semiconductor elements.

27. The assembly of claim 26 , wherein the dielectric material is a polymeric material.

28. The assembly of claim 23 , wherein the electrically conductive element substantially fills the first and second openings of each of the first and second semiconductor elements.

29. The assembly of claim 23 , further comprising a metal layer lining the first and second openings of the second semiconductor element, and a dielectric layer overlying the metal layer within the first and second openings, the metal layer extending at least partially through the conductive pad of the second semiconductor element.

30. The assembly of claim 29 , wherein the metal layer extends through the entire thickness of the conductive pad of the second semiconductor element.

31. The assembly of claim 23 , wherein the second semiconductor element includes a plurality of active semiconductor devices.

32. A system comprising an assembly according to claim 23 and one or more other electronic components electrically connected to the assembly.

33. A system as claimed in claim 32 further comprising a housing, the assembly and the other electronic components being mounted to the housing.

34. An assembly comprising:

a first semiconductor element stacked atop a second semiconductor element, each of the first and second semiconductor elements having a front surface, a rear surface remote from the front surface, and a conductive pad exposed at the front surface and separated from a semiconductor layer of the semiconductor element by a dielectric layer, a first opening extending from the rear surface towards the front surface, and a second opening extending from the first opening and exposing a portion of the dielectric layer adjacent to the respective conductive pad, the first and second openings having respective interior surfaces extending at angles relative to each other, the conductive pad of the first semiconductor element overlying the conductive pad of the second semiconductor element;

a dielectric region at least substantially filling the first and second openings;

a third opening extending through the dielectric region within the first and second openings and extending through the conductive pad of at least the first semiconductor element; and

an electrically conductive element extending through the third opening, the conductive element electrically connecting the conductive pads.

35. The assembly of claim 34 , wherein the conductive pad of at least the first semiconductor element has an inner surface exposed within the second opening, the inner surface extending from a bottom surface of the conductive pad adjacent the second opening to a top surface thereof remote from the bottom surface, the conductive element contacting the inner surface of the conductive pad of at least the first semiconductor element.

36. The assembly of claim 34 , wherein at least a portion of the conductive element does not conform to a contour of the respective interior surfaces of the first and second openings in the respective first and second semiconductor elements.

37. The assembly of claim 34 , wherein the dielectric region is a polymeric material.

38. The assembly of claim 34 , wherein the electrically conductive element substantially fills the third opening.

39. The assembly of claim 34 , further comprising a metal layer lining the third opening, and a dielectric layer overlying the metal layer within the third opening, the metal layer extending at least partially through the conductive pad of the second semiconductor element.

40. The assembly of claim 39 , wherein the metal layer extends through the entire thickness of the conductive pad of the second semiconductor element.

41. The assembly of claim 34 , wherein the second semiconductor element includes a plurality of active semiconductor devices.

42. A system comprising an assembly according to claim 34 and one or more other electronic components electrically connected to the assembly.

43. A system as claimed in claim 42 further comprising a housing, the assembly and the other electronic components being mounted to the housing.

44. The method of claim 12 , wherein the interior surfaces of the respective first and second openings extend at nonzero angles relative to each other.

45. The method of claim 22 , wherein the interior surfaces of the respective first and second openings extend at nonzero angles relative to each other.

46. The assembly of claim 34 , wherein the interior surfaces of the respective first and second openings extend at nonzero angles relative to each other.

47. The method of claim 1 , wherein the interior surface of at least one of the first and second openings is curved.

48. The assembly of claim 23 , wherein the interior surface of at least one of the first and second openings is curved.

49. The method of claim 1 , wherein at a junction of the interior surfaces of the first and second openings, the interior surface of the first opening converges in a direction extending from the rear surface to the front surface, and the interior surface of the second opening diverges in said direction.

50. The assembly of claim 23 , wherein at a junction of the interior surfaces of the first and second openings, the interior surface of the first opening converges in a direction extending from the rear surface to the front surface, and the interior surface of the second opening diverges in said direction.