IP Library Granted Patent US 8,072,057
Granted Patent B2
US 8,072,057 · App. 12/890,058 · Granted Dec 6, 2011

Semiconductor device and method of fabrication

Assignee: Panasonic Corporation
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,072,057
App. No.
12/890,058
Granted
Dec 6, 2011
Kind
B2
Abstract

A semiconductor device includes a first die pad, a first semiconductor chip provided on the first die pad, a second die pad, a second semiconductor chip provided on the second die pad, and a sealing resin made of a first resin material, sealing the first die pad, the first semiconductor chip, the second die pad and the second semiconductor chip. A lower surface of the first semiconductor chip is connected to the first die pad. A first portion of a lower surface of the second semiconductor chip is connected to the second die pad, and a second portion not connected to the second die pad of the lower surface of the second semiconductor chip is connected to an upper surface of the first semiconductor chip via a second resin material different from the first resin material.

Claims (15)

1. A semiconductor device comprising:

a first die pad;

a first semiconductor chip provided on the first die pad;

a second die pad;

a second semiconductor chip provided on the second die pad; and

a sealing resin, sealing the first die pad, the first semiconductor chip, the second die pad and the second semiconductor chip,

wherein a lower surface of the first semiconductor chip is connected to the first die pad, and

a first portion of a lower surface of the second semiconductor chip is connected to the second die pad, and a second portion not connected to the second die pad of the lower surface of the second semiconductor chip is connected to an upper surface of the first semiconductor chip,

the lower surface of the first die pad is exposed from the sealing resin.

2. The semiconductor device of claim 1 , wherein

the first and second die pads are electrically isolated from each other, and

the first and second die pads are provided at positions different from each other in a vertical direction.

3. The semiconductor device of claim 1 , wherein one of the first and second die pads is grounded.

4. The semiconductor device of claim 1 , wherein

the first semiconductor chip has a high heat generation circuit region having a relatively high amount of heat generated during a circuit operation and a low heat generation circuit region having a relatively low amount of heat generated during the circuit operation.

Assignments (6)
CHANGE OF NAME Recorded Nov 19, 2025
From: TESSERA ADVANCED TECHNOLOGIES, INC.
To: ADEIA SEMICONDUCTOR ADVANCED TECHNOLOGIES INC.
Reel/Frame 073635/0304 →
RELEASE OF SECURITY INTEREST Recorded Jun 11, 2020
From: ROYAL BANK OF CANADA
To: TESSERA, INC.; INVENSAS BONDING TECHNOLOGIES, INC. (F/K/A ZIPTRONIX, INC.); FOTONATION CORPORATION (F/K/A DIGITALOPTICS CORPORATION AND F/K/A DIGITALOPTICS CORPORATION MEMS); INVENSAS CORPORATION; TESSERA ADVANCED TECHNOLOGIES, INC; DTS, INC.; DTS LLC; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
Reel/Frame 052920/0001 →
SECURITY INTEREST Recorded Jun 1, 2020
From: ROVI SOLUTIONS CORPORATION; ROVI TECHNOLOGIES CORPORATION; ROVI GUIDES, INC.; TIVO SOLUTIONS INC.; VEVEO, INC.; INVENSAS CORPORATION; INVENSAS BONDING TECHNOLOGIES, INC.; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: BANK OF AMERICA, N.A.
Reel/Frame 053468/0001 →
SECURITY INTEREST Recorded Dec 2, 2016
From: INVENSAS CORPORATION; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; ZIPTRONIX, INC.; DIGITALOPTICS CORPORATION; DIGITALOPTICS CORPORATION MEMS; DTS, LLC; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: ROYAL BANK OF CANADA, AS COLLATERAL AGENT
Reel/Frame 040797/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 25, 2016
From: PANNOVA SEMIC, LLC
To: TESSERA ADVANCED TECHNOLOGIES, INC.
Reel/Frame 037581/0466 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 7, 2015
From: PANASONIC CORPORATION
To: PANNOVA SEMIC, LLC
Reel/Frame 036065/0273 →
Priority Claims (2)
JP 2008-123674 · May 9, 2008 · national
JP 2009-029623 · Feb 12, 2009 · national
Continuity (2)
Division 12425682 · Apr 17, 2009
Related Publication 20110012250A1 · Jan 20, 2011