Granted Patent B2

US 8,917,582 · App. 12/916,425 · Granted Dec 23, 2014

Abstract

Claims (48)

1. An echo canceller, comprising:

an analog to digital converter (ADC) configured to convert, at a first clock frequency, a received analog error signal to a digital error signal;

a digital interpolation filter comprising a plurality of sub-filters operating at the first clock frequency, wherein the digital interpolation filter is configured to process a first digital echo estimate signal, generated based on the digital error signal, in parallel using the plurality of sub-filters to generate a plurality of interpolated first digital echo estimate signals; and

a multiplexer configured to combine the interpolated first digital echo estimate signals to generate a second digital echo estimate signal at a second clock frequency greater than the first clock frequency.

2. The echo canceller of claim 1 , wherein the second clock frequency comprises a frequency at least double that of the first clock frequency.

3. The echo canceller of claim 1 , further comprising:

a digital-to-analog converter (DAC), coupled to the multiplexer, configured to convert, at the second clock frequency, the second digital echo estimate signal to an analog echo estimate signal; and

a subtractor, coupled to the DAC, configured to subtract the analog echo estimate signal from an incoming signal having an echo signal to generate an analog error signal with a reduced echo signal.

4. The echo canceller of claim 1 , further comprising:

an adaptive filter, coupled to the digital interpolation filter, configured to generate the first digital echo estimate signal based on a local transmit signal; and

a least means squared (LMS) unit configured to:

reduce a correlation between the digital error signal and the local transmit signal, and

generate adaptive filter coefficient updates based on the correlation.

5. A method, comprising:

processing, at a first clock frequency, a first digital echo estimate signal using parallel paths to generate a plurality of interpolated first digital echo estimate signals; and

combining the interpolated first digital echo estimate signals to generate a second digital echo estimate signal at a second clock frequency greater than the first clock frequency; and

generating an analog echo estimate signal based on the second digital echo estimate signal with a digital to analog converter (DAC) unit operating at the second clock frequency.

6. The method of claim 5 , wherein the second clock frequency comprises a frequency at least double that of the first clock frequency.

7. The method of claim 5 , further comprising:

generating an analog error signal with a reduced echo signal by subtracting the analog echo estimate signal from an incoming signal having an echo signal.

8. The method of claim 5 , further comprising:

generating the first digital echo estimate signal based on a local transmit signal;

reducing a correlation between a digital error signal and the local transmit signal using a least means squared (LMS) algorithm; and

generating adaptive filter coefficient updates based on the correlation.

9. The method of claim 7 , further comprising:

converting, at the first clock frequency, the analog error signal to a digital error signal.

10. An echo canceller, comprising:

a filter, wherein the filter comprises a plurality of sub-filters configured to operate at a first frequency, and wherein the filter is configured to process an echo estimate in parallel using the plurality of sub-filters to generate a plurality of additional echo estimates;

a multiplexer configured to combine the plurality of additional echo estimates to generate an output signal at a second frequency greater than the first frequency, wherein a ratio of the second frequency to the first frequency is determined based on a number of the plurality of sub-filters;

a subtractor coupled to the multiplexer, wherein the subtractor is configured to:

receive the output signal and an incoming signal, and

subtract the output signal from the incoming signal to generate a received error signal; and

an analog to digital converter (ADC) coupled to an output of the subtractor.

11. The echo canceller of claim 10 , further comprising:

a second filter coupled to the filter, wherein the second filter is configured to generate the echo estimate based on a local transmit signal.

12. The echo canceller of claim 11 , further comprising:

a least mean square (LMS) unit coupled to the subtractor, wherein the LMS unit is configured to generate coefficient updates for the second filter based on the received error signal.

13. The echo canceller of claim 10 , further comprising:

a digital signal processing (DSP) unit coupled to the subtractor, wherein the DSP unit is configured to process the received error signal.

14. The echo canceller of claim 11 , further comprising:

an analog to digital converter (ADC) coupled to an output of the subtractor and to an input of the second filter.

15. The echo canceller of claim 14 , wherein a frequency of the ADC is approximately equal to the first frequency.

16. The echo canceller of claim 15 , wherein each of the plurality of sub-filters is configured to cancel a portion of the echo estimate across a predetermined frequency range.

17. The echo canceller of claim 11 , wherein the second filter is further configured to reduce a correlation between the incoming signal and the local transmit signal.

18. The echo canceller of claim 1 , wherein the plurality of sub-filters are arranged in a parallel configuration.

19. The echo canceller of claim 1 , wherein a ratio of the second clock frequency to the first clock frequency is determined by a number of the plurality of sub-filters.

20. The echo canceller of claim 3 , wherein a ratio of the second clock frequency to the first clock frequency is determined by a number of the plurality of sub-filters.

21. The method of claim 5 , wherein a ratio of the second clock frequency to the first clock frequency is determined by a number of the parallel paths.

Assignments (8)