Compact instruction format for content search systems

1. A method for compiling a source regular expression into a plurality of microprogram instructions for controlling a content search system, comprising:

parsing the source regular expression into one or more sub-expressions, comprising an inexact sub-expression associated with an inexact pattern;

compiling the inexact sub-expression into the plurality of microprogram instructions such that the plurality of microprogram instructions form a contiguous group of microprogram instructions; and

storing the contiguous group of microprogram instructions into contiguous locations of an instruction memory.

2. The method of claim 1 , wherein the parsing differentiates an exact sub-expression from the inexact sub-expression.

3. The method of claim 2 , wherein the inexact sub-expression comprises at least one of: a “*” quantifier, a “?” quantifier, a “{n}” quantifier, a “{n,}” quantifier, and a “{n,m}” quantifier.

4. The method of claim 1 , wherein at least one of the contiguous group microprogram instructions comprises an opcode, a next instruction address, and a fetch length value.

5. The method of claim 4 , wherein the fetch length value indicates a number of instructions to be fetched from contiguous locations in the instruction memory.

6. The method of claim 4 , wherein the plurality of microprogram instructions are pre-fetched from the instruction memory into a cache memory in response to the next instruction address and the fetch length value.

7. The method of claim 1 , wherein a set of microprogram instructions are pre-fetched from the instruction memory based on one or more operands of a first microprogram instruction.

8. The method of claim 7 , wherein the first microprogram instruction comprises an opcode operand, an offset operand, and a fetch length operand.

9. A system for compiling a source regular expression into a plurality of microprogram instructions for controlling a content search system, comprising:

means for parsing the source regular expression into one or more sub-expressions, comprising an inexact sub-expression associated with an inexact pattern;

means for compiling the inexact sub-expression into the plurality of microprogram instructions such that the plurality of microprogram instructions form a contiguous group of microprogram instructions; and

means for storing the contiguous group of microprogram instructions into contiguous locations of an instruction memory.

10. The system of claim 9 , wherein the parsing differentiates an exact sub-expression from the inexact sub-expression.

11. The system of claim 10 , wherein the inexact sub-expression comprises at least one of: a “*” quantifier, a “?” quantifier, a “{n}” quantifier, a “{n,}” quantifier, and a “{n,m}” quantifier.

12. The system of claim 9 , wherein at least one of the contiguous group microprogram instructions comprises an opcode, an offset value, and a fetch length value.

13. The system of claim 12 , wherein the fetch length value indicates a number of instructions to be fetched from contiguous locations in the instruction memory.

14. The system of claim 12 , wherein the plurality of microprogram instructions are pre-fetched from the instruction memory into a cache memory in response to a next instruction address and the fetch length value.

15. The system of claim 9 , wherein a set of microprogram instructions are pre-fetched from the instruction memory based on one or more operands of a first microprogram instruction.

16. The system of claim 15 , wherein the first microprogram instruction comprises an opcode operand, an offset operand, and a fetch length operand.

17. A computer program product embodied on a tangible computer readable medium for storing non-transitory data for compiling a source regular expression into a plurality of microprogram instructions for controlling a content search system, the computer program product configured to:

parse the source regular expression into one or more sub-expressions, comprising an inexact sub-expression associated with an inexact pattern;

compile the inexact sub-expression into the plurality of microprogram instructions such that the plurality of microprogram instructions form a contiguous group of microprogram instructions; and

store the contiguous group of microprogram instructions into contiguous locations of an instruction memory.

18. The computer program product of claim 17 , wherein the parsing differentiates an exact sub-expression from the inexact sub-expression.

19. The computer program product of claim 18 , wherein the inexact sub-expression comprises at least one of: a “*” quantifier, a “?” quantifier, a “{n}” quantifier, a “{n,}” quantifier, and a “{n,m}” quantifier.

20. The computer program product of claim 17 , wherein at least one of the plurality of microprogram instructions comprises an opcode, an offset value, and a fetch length value.

21. The computer program product of claim 20 , wherein the fetch length value indicates a number of instructions to be fetched from contiguous locations in the instruction memory.

22. The computer program product of claim 20 , wherein the plurality of microprogram instructions are pre-fetched from the instruction memory into a cache memory in response to a next instruction address and the fetch length value.

23. The computer program product of claim 17 , wherein a set of microprogram instructions are pre-fetched from the instruction memory based on one or more operands of a first microprogram instruction.

24. The computer program product of claim 23 , wherein the first microprogram instruction comprises an opcode operand, an offset operand, and a fetch length operand.