Variable resistive memory punchthrough access method
View Patent ↗Variable resistive punchthrough access methods are described. The methods include switching a variable resistive data cell from a high resistance state to a low resistance state by passing a write current through the magnetic tunnel junction data cell in a first direction. The write current is provided by a transistor being electrically coupled to the variable resistive data cell and a source line. The write current passes through the transistor in punchthrough mode.
1. A method comprising:
applying a voltage across a source region and a drain region of a metal-oxide-semiconductor field effect transistor that is sufficient to merge a source depletion region and a drain depletion region of the metal-oxide-semiconductor field effect transistor and conduct a write current through the metal-oxide-semiconductor field effect transistor;
switching a variable resistive data cell from a high resistance state to a low resistance state by passing the write current through the variable resistive data cell in a first direction, the write current provided by the metal-oxide-semiconductor field effect transistor being electrically coupled to the variable resistive data cell.
2. A method according to claim 1 , further comprising switching the variable resistive data cell from the low resistance state to the high resistance state by passing the write current through the variable resistive data cell in a second direction opposing the first direction, the write current provided by the metal-oxide-semiconductor field effect transistor.
3. A method according to claim 1 , wherein the metal-oxide-semiconductor field effect transistor is a NMOS transistor or a PMOS transistor.
4. A method according to claim 1 , wherein the variable resistive data cell is a magnetic tunnel junction data cell.
5. A method according to claim 1 , wherein the write current in the first direction has about the same magnitude as the write current in the second direction.
6. A method according to claim 3 , wherein the magnetic tunnel junction data cell is a spin-transfer torque data cell.
7. A method according to claim 1 , further comprising passing a read current through the variable resistive data cell by activating a gate of the metal-oxide-semiconductor field effect transistor.
8. A method according to claim 1 , further comprising passing a read current through the variable resistive data cell, the read current formed by applying a voltage across a source region and a drain region of a metal-oxide-semiconductor field effect transistor that is sufficient to merge a source depletion region and a drain depletion region of the metal-oxide-semiconductor field effect transistor and conduct the read current through the metal-oxide-semiconductor field effect transistor.
9. A method according to claim 1 , wherein the write current in the first direction and the write current in the second direction is formed by a voltage difference across a source region and drain region of the transistor having a magnitude equal to or greater than a punchthrough voltage for the transistor.
10. A method comprising:
switching a variable resistive data cell from a high resistance state to a low resistance state by passing a write current through the variable resistive data cell in a first direction, the write current provided by a metal-oxide-semiconductor field effect transistor being electrically coupled to the variable resistive data cell, the write current passing through the metal-oxide-semiconductor field effect transistor in punchthrough mode.
11. A method according to claim 10 , further comprising switching the variable resistive data cell from the low resistance state to the high resistance state by passing the write current through the variable resistive data cell in a second direction opposing the first direction, the write current provided by the metal-oxide-semiconductor field effect transistor operating in punchthrough mode.
12. A method according to claim 10 , wherein the metal-oxide-semiconductor field effect transistor is a NMOS transistor or a PMOS transistor.
13. A method according to claim 10 , wherein the variable resistive data cell is a magnetic tunnel junction data cell.
14. A method according to claim 10 , wherein the write current in the first direction has about the same magnitude as the write current in the second direction.
15. A method according to claim 13 , wherein the magnetic tunnel junction data cell is a spin-transfer torque data cell.
16. A method according to claim 10 , further comprising passing a read current through the variable resistive data cell by activating a gate of the metal-oxide-semiconductor field effect transistor.
17. A method comprising:
applying a voltage across a source region and a drain region of a first metal-oxide-semiconductor field effect transistor that is sufficient to merge a source depletion region and a drain depletion region of the first metal-oxide-semiconductor field effect transistor and conduct a write current through the first metal-oxide-semiconductor field effect transistor;
activating a common metal-oxide-semiconductor field effect transistor to allow the write current to pass through the common metal-oxide-semiconductor field effect transistor, the common metal-oxide-semiconductor field effect transistor electrically coupled to a source line and the first variable resistive data cell, the common metal-oxide-semiconductor field effect transistor electrically coupled to a second variable resistive data cell.
18. A method according to claim 17 wherein the first and second variable resistive data cells are spin-transfer torque data cells.
19. A method according to claim 17 wherein the write current selectively passes through the first and second variable resistive data cells.
20. A method according to claim 17 wherein the common metal-oxide-semiconductor field effect transistor is electrically connected to three or more variable resistive data cells.