IP Library Granted Patent US 8,637,360
Granted Patent B2
US 8,637,360 · App. 12/950,202 · Granted Jan 28, 2014

Power devices with integrated protection devices: structures and methods

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Quick Facts
Patent No.
US 8,637,360
App. No.
12/950,202
Granted
Jan 28, 2014
Kind
B2
Abstract

Exemplary embodiments provide structures and methods for power devices with integrated clamp structures. The integration of clamp structures can protect the power device, e.g., from electrical overstress (EOS). In one embodiment, active devices can be formed over a substrate, while a clamp structure can be integrated outside the active regions of the power device, for example, under the active regions and/or inside the substrate. Integrating clamp structure outside active regions of power devices can maximize the active area for a given die size and improve robustness of the clamped device since the current will spread in the substrate by this integration.

Claims (38)

1. A method of manufacturing an active device comprising:

providing a substrate comprising an epitaxial layer disposed on an underlying layer;

forming an active region of an active device over the substrate;

forming a first trench and a second trench each through the active region and on the substrate;

forming a first doped region in the epitaxial layer of the substrate, the first doped region coupled to the first trench;

forming a second doped region in the epitaxial layer of the substrate, the second doped region coupled to the second trench;

filling the first trench with a conductive material to form a first trench electrode;

filling the second trench with a conductive material to form a second trench electrode;

forming a source electrode of the active device electrically, the source electrode coupled to the first trench electrode; and

forming a drain electrode of the active device electrically, the drain electrode coupled to the second trench electrode.

2. The method of claim 1 , further comprising forming a dielectric layer or a trench electrode barrier layer on surfaces of the first trench or the second trench prior to filling with the conductive material.

3. The method of claim 1 , further comprising

forming a dielectric layer on sidewalls of each of the first trench and the second trench;

forming a trench electrode barrier layer on each surface of the first trench having the dielectric layer and of the second trench having the dielectric layer; and

filling the first trench having the trench electrode barrier layer with the conductive material to form the first trench electrode; and

filling the second trench having the trench electrode barrier layer with the conductive material to form the second trench electrode.

4. The method of claim 1 , wherein forming an active region of an active device over the substrate comprises forming a GaN-based active region.

5. The method of claim 1 , wherein forming a first trench and a second trench comprises:

forming the first trench through the active region and on the epitaxial layer; and

forming the second trench through the active region and on the underlying layer.

6. A method of manufacturing a high electron mobility transistor (HEMT) comprising:

providing a multi-layer substrate comprising a first layer disposed on a second layer;

forming a HEMT active region over the substrate;

forming a first trench through the HEMT active region to expose a portion of the first layer of the substrate;

doping the exposed portion of the first layer to form a first doped region in the first layer of the substrate;

forming a second trench through the HEMT active region to expose a second portion of one of the first layer or the second layer of the substrate;

filling the first trench with a conductive material to form a first trench electrode;

filling the second trench with a conductive material to form a second trench electrode;

forming an HEMT source electrode electrically coupled to the first trench electrode; and

forming an HEMT drain electrode electrically coupled to the second trench electrode.

7. The method of claim 6 , further comprising forming a dielectric layer or a trench electrode barrier layer on surfaces of the first trench or the second trench prior to filling with the conductive material.

8. The method of claim 6 , further comprising

forming a dielectric layer on sidewalls of each of the first trench and the second trench;

forming a trench electrode barrier layer on each surface of the first trench having the dielectric layer and of the second trench having the dielectric layer; and

filling the first trench having the trench electrode barrier layer with the conductive material to form the first trench electrode; and

filling the second trench having the trench electrode barrier layer with the conductive material to form the second trench electrode.

9. The method of claim 6 , wherein forming an HEMT active region comprises forming a GaN-based HEMT active region.

10. The method of claim 6 , wherein the first trench is a shallow trench and the second trench is a deep trench.

Assignments (4)
MERGER Recorded Jun 16, 2016
From: TRIQUINT SEMICONDUCTOR, INC.
To: QORVO US, INC.
Reel/Frame 039050/0193 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 30, 2014
From: INTERSIL AMERICAS LLC
To: TRIQUINT SEMICONDUCTOR, INC.
Reel/Frame 032794/0948 →
CHANGE OF NAME Recorded Mar 25, 2014
From: INTERSIL AMERICAS INC.
To: INTERSIL AMERICAS LLC
Reel/Frame 032524/0499 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 19, 2010
From: HEBERT, FRANCOIS
To: INTERSIL AMERICAS INC.
Reel/Frame 025377/0931 →