Enhanced stacked microelectronic assemblies with central contacts and vias connected to the central contacts
The microelectronic assembly includes a first microelectronic element having a front surface, a plurality of contacts exposed at the front surface, and a rear surface remote from the front surface; a second microelectronic element having a front surface facing the rear surface of the first microelectronic element and projecting beyond an edge of the first microelectronic element, the second microelectronic element having a plurality of contacts exposed at its front surface; a dielectric region overlying the front surfaces of the microelectronic elements, the dielectric region having a major surface facing away from the microelectronic elements; metallized vias within openings in the dielectric region extending from the plurality of contacts of the first and second microelectronic elements; and leads extending along a major surface of the dielectric region from the vias to terminals exposed at the major surface.
1. A microelectronic assembly, comprising:
a first microelectronic element having a front surface, a plurality of contacts exposed at the front surface, and a rear surface remote from the front surface;
a second microelectronic element having a front surface facing the rear surface of the first microelectronic element and projecting beyond an edge of the first microelectronic element, the second microelectronic element having a plurality of contacts exposed at its front surface;
a dielectric region overlying the front surfaces of the microelectronic elements, the dielectric region having a major surface facing away from the microelectronic elements;
metallized vias within openings in the dielectric region extending from the plurality of contacts of the first and second microelectronic elements; and
leads extending along the major surface of the dielectric region from the vias to terminals exposed at the major surface.
2. The microelectronic assembly of claim 1 , wherein the at least one of the first microelectronic element or the second microelectronic element includes a dynamic random access memory (DRAM) storage.
3. The microelectronic assembly of claim 1 , further comprising solder balls connected to the terminals.
4. The microelectronic assembly of claim 1 , further comprising an overmold overlying the rear surface and at least partially overlies an edge surface of the first microelectronic element.
5. The microelectronic assembly of claim 4 , wherein the second microelectronic element has a rear surface remote from a front surface thereof, and wherein an overmold overlies its rear surface and at least partially overlies an edge surface of the second microelectronic element.
6. The microelectronic assembly of claim 1 , wherein the metallized vias are formed by depositing a metal at least within the openings.
7. The microelectronic assembly of claim 1 , further comprising a support member disposed between the second microelectronic element and the face of the microelectronic assembly.
8. A stacked microelectronic assembly including at least first and second and second microelectronic assemblies, each as claimed in claim 1 , the second microelectronic assembly being stacked atop the first microelectronic assembly and electrically connected thereto.
9. The microelectronic assembly of claim 8 , wherein the first and second stacked microelectronic assemblies are electrically connected through electrically conductive columns extending between a front face of the second microelectronic assembly and the rear face of the first microelectronic assembly facing such front face.
10. The microelectronic assembly of claim 9 , wherein each of the electrically conductive columns includes a substantially rigid metal post.
11. A system comprising an assembly as in claim 1 and one or more other electronic components electrically connected to the assembly.
12. The system according to claim 11 , further comprising a housing, the assembly and the other electronic components being mounted to the housing.
13. A microelectronic assembly, comprising:
a first microelectronic element having a front surface, a plurality of contacts exposed at the front surface, and a rear surface remote from the front surface;
a second microelectronic element having a front surface facing the rear surface of the first microelectronic element and projecting beyond an edge of the first microelectronic element, the second microelectronic element having a plurality of contacts exposed at its front surface;
a dielectric region overlying the front surfaces of the microelectronic elements, the dielectric region having a major surface facing away from the microelectronic elements;
metal posts extending from the plurality of contacts of the second microelectronic element;
metallized vias within openings in the dielectric region extending from the plurality of metal posts; and
leads extending along the major surface of the dielectric region from the vias to terminals exposed at the major surface, the leads electrically connected to the contacts of the first and second microelectronic elements, including at least some leads extending from the vias.
14. The microelectronic assembly as claimed in claim 13 , wherein at least some of the metal posts extend from the plurality of contacts of the first microelectronic element, and the leads include at least some leads extending to metalized vias extending from the at least some metal posts.
15. A method of making microelectronic assemblies, comprising:
placing a spacer and a first microelectronic element face down on a carrier with an opening between them, the first microelectronic element including a plurality of contacts;
placing a second microelectronic element face down on the spacer and the first microelectronic element such that contacts of the second microelectronic element are exposed within the opening;
forming an overmold overlying rear faces of the first and second microelectronic elements;
removing the carrier therefrom;
forming a dielectric region overlying front faces of the first and second microelectronic elements, the dielectric region having a major surface facing away from the microelectronic elements;
forming openings through the dielectric region to expose the contacts of the first and second microelectronic elements; and
depositing metal to fill the openings and form traces extending along the major surface of the dielectric region.
16. The method as claimed in claim 15 , wherein the step of depositing metal forms terminals at the major surface connected to the traces.
17. The method as claimed in claim 16 , wherein the method further comprises attaching solder balls to the terminals.
18. The method as claimed in claim 15 , wherein the step of forming the overmold includes forming the overmold in a wafer or panel format.
19. The method according to claim 18 , wherein performing all the steps forms a structure containing a group of microelectronic assemblies on a wafer or panel, each microelectronic assembly including the first microelectronic assembly, the spacer, the second microelectronic assembly and the dielectric region.
20. The method according to claim 19 , further comprising separating the structure into individual microelectronic assemblies.
21. The method as claimed in claim 15 , wherein the step of depositing the metal includes depositing metal onto the contacts of the microelectronic elements.
22. The method as claimed in claim 15 , wherein the step of forming the dielectric region includes placing a partially cured dielectric element overlying the front surfaces of the microelectronic elements and heating the dielectric element to cause material of the dielectric element to flow.
23. The method as claimed in claim 15 , wherein the step of forming the dielectric region includes at least one of spin-coating, laminating, printing, dispensing or molding a dielectric material onto the microelectronic elements.
24. The method as claimed in claim 15 , wherein depositing includes plating the metal.
25. The method as claimed in 15 , wherein the step of forming the metalized vias and traces includes selectively depositing the metal onto trace areas of the major surface to form the plurality of traces.
26. The method as claimed in 15 , wherein the step of metalizing the dielectric region further includes patterning the plated metal on the major surface to form the plurality of traces.