IP Library Granted Patent US 8,595,562
Granted Patent B2
US 8,595,562 · App. 13/014,318 · Granted Nov 26, 2013

Semiconductor integrated circuit, operating method of semiconductor integrated circuit, and debug system

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Quick Facts
Patent No.
US 8,595,562
App. No.
13/014,318
Granted
Nov 26, 2013
Kind
B2
Abstract

A current measurement unit measuring power supply currents each consumed in a plurality of circuit blocks of which at least one of the circuit blocks includes a processor, and outputting the measurement result as the power supply current values. A selection unit selecting at least one of the power supply current values according to selection information. A trace buffer sequentially holding the power supply current values being selected by the selection unit together with execution information of the processor, and sequentially outputting the held information. By selecting the power supply current values of the circuit blocks required for debugging according to the selection information, the number of external terminals of a semiconductor integrated circuit required for the debugging which includes tracing the power supply current values may be reduced. As a result, a chip size of the semiconductor integrated circuit with a debug function may be reduced.

Claims (31)

1. A semiconductor integrated circuit, comprising:

a current measurement unit including a plurality of ammeters coupled to power supply lines which are coupled to a plurality of circuit blocks of which at least one of the circuit blocks includes a processor, measuring power supply currents each consumed in the plurality of circuit blocks by the ammeters corresponding to the plurality of circuit blocks, and outputting a measurement result as power supply current values;

a selection unit selecting at least one of the power supply current values according to selection information; and

a trace buffer sequentially holding the power supply current values being selected by the selection unit together with execution history information indicating an execution history of the processor as trace information, and sequentially outputting the trace information being held.

2. The semiconductor integrated circuit according to claim 1 , wherein

the selection unit includes an adder which adds the power supply current values being selected according to the selection information and outputs a summation of the power supply current values being added to the trace buffer.

3. The semiconductor integrated circuit according to claim 1 , further comprising

a counter cyclically generating the selection information, wherein

the selection unit cyclically selects the power supply current values according to the selection information and outputs the selected power supply current values to the trace buffer.

4. The semiconductor integrated circuit according to claim 3 , wherein

the trace buffer holds the selection information together with one of the selected power supply current values as identification information indicating one of the circuit blocks which corresponds to the one of the selected power supply current values.

5. An operating method of a semiconductor integrated circuit, comprising:

measuring power supply currents each consumed in a plurality of circuit blocks of which at least one of the circuit blocks includes a processor by a plurality of ammeters coupled to power supply lines which are coupled to the plurality of circuit blocks;

outputting a measurement result as power supply current values;

selecting at least one of the power supply current values according to selection information;

sequentially holding the power supply current values being selected to a trace buffer together with execution history information indicating an execution history of the processor as trace information; and

sequentially outputting the trace information being held.

6. The operating method of the semiconductor integrated circuit according to claim 5 , comprising:

adding the power supply current values being selected according to the selection information; and

outputting a summation of the power supply current values being added to the trace buffer.

7. The operating method of the semiconductor integrated circuit according to claim 5 , comprising:

cyclically selecting the power supply current values according to the selection information; and

outputting the selected power supply current values to the trace buffer.

8. The operating method of the semiconductor integrated circuit according to claim 7 , comprising

holding the selection information together with one of the selected power supply current values as identification information indicating one of the circuit blocks which corresponds to the one of the selected power supply current values.

9. A debugging system comprising

a semiconductor integrated circuit including:

a current measurement unit including a plurality of ammeters coupled to power supply lines which are coupled to a plurality of circuit blocks of which at least one of the circuit blocks includes a processor, measuring power supply currents each consumed in the plurality of circuit blocks by the ammeters corresponding to the plurality of circuit blocks, and outputting a measurement result as power supply current values;

a selection unit selecting at least one of the power supply current values according to selection information; and

a trace buffer sequentially holding the power supply current values being selected by the selection unit together with execution history information indicating an execution history of the processor as trace information, and sequentially outputting the trace information being held, and

an external debugging apparatus supplying the selection information input from outside of the system to the semiconductor integrated circuit, reading the trace information held in the trace buffer, and outputting the trace information as execution history information of the circuit blocks.

Assignments (6)
RELEASE OF SECURITY INTEREST Recorded Mar 16, 2022
From: MUFG UNION BANK, N.A.
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 059410/0438 →
CORRECTIVE ASSIGNMENT TO CORRECT THE 8647899 PREVIOUSLY RECORDED ON REEL 035240 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTERST. Recorded Nov 3, 2020
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 058002/0470 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN INTELLECTUAL PROPERTY Recorded Oct 28, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: MUFG UNION BANK, N.A.
Reel/Frame 050896/0366 →
SECURITY INTEREST Recorded Mar 21, 2015
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 035240/0429 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 11, 2013
From: FUJITSU SEMICONDUCTOR LIMITED
To: SPANSION LLC
Reel/Frame 031205/0461 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 31, 2011
From: SATO, TAKASHI; SARUWATARI, TOSHIAKI; RYU, KEN
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 025724/0110 →