IP Library Granted Patent US 8,792,348
Granted Patent B1
US 8,792,348 · App. 13/034,570 · Granted Jul 29, 2014

Serial link interface power control method and apparatus with selective idle data discard

Inventor: Shankar Channabasappa (San Jose, CA)
Assignee: Netlogic Microsystems, Inc.
H04L43/0811
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,792,348
App. No.
13/034,570
Granted
Jul 29, 2014
Kind
B1
Abstract

A receiver circuit for coupling to a serial link is disclosed. The receiver circuit comprises a data buffer and serial interface circuitry. The serial interface circuitry receives serialized packet words and processes the serial words for input to the data buffer. The serial interface circuitry includes word detection logic to detect predefined control words and discard logic to selectively inhibit forwarding of one or more of the predefined control words to the data buffer.

Claims (36)

1. A receiver circuit for coupling to a serial link, the receiver circuit comprising:

a data buffer;

serial interface circuitry configured to receive serial packet words and process the serial packet words for input to the data buffer, the serial interface circuitry including word detection logic configured to detect control words and data words, and

gating logic configured to:

process the control words and the data words, wherein the control words are forwarded to the data buffer based on a previously detected control word, and

selectively inhibit forwarding the data words to the data buffer.

2. The receiver circuit of claim 1 , wherein the serial interface circuitry receives the serial packet words in accordance with an Interlaken packet protocol.

3. The receiver circuit of claim 1 , wherein the serial interface circuitry further includes a bypass path to route information associated with the control words.

4. The receiver circuit of claim 3 , wherein the information routed on the bypass path includes flow control information.

5. The receiver circuit of claim 3 , wherein the information routed on the bypass path comprises CRC information.

6. The receiver circuit of claim 3 , wherein the control words comprise idle control words.

7. The receiver circuit of claim 1 , wherein the data buffer comprises a first-in-first-out (FIFO) circuit.

8. A method comprising:

receiving serial packet words;

converting the serial packet words to parallel words;

detecting control words and data words from among the parallel words;

processing the control words and the data words, wherein the control words are forwarded to data processing circuitry based on a previously detected control word, and

selectively inhibiting forwarding the data words to the data processing circuitry.

9. The method of claim 8 , wherein the control words comprise idle control words.

10. The method of claim 8 , wherein processing the control words is based on whether the previously detected control word was an idle control word.

11. The method of claim 8 , further including extracting flow control information from the control words.

12. The method of claim 8 , farther including extracting CRC information from the control words.

13. A system comprising:

a first electronic device having a transmitter for transmitting serial data in accordance with a serial protocol;

a serial link having one end coupled to the first electronic device to route the serial data; and

a second electronic device having a receiver circuit coupled to a second end of the serial link to receive the serial data, the receiver circuit including:

a data buffer;

serial interface circuitry configured to receive the serial data as packet words and process the packet words for input to the data buffer, the serial interface circuitry including word detection logic configured to detect control words and data words, and

gating logic configured to:

process the control words and the data words, wherein the control words are forwarded to the data buffer based on a previously detected control word, and

selectively inhibit forwarding the data words to the data buffer.

14. The system of claim 13 , further comprising a plurality of serial links disposed between the first and second electronic devices.

15. The system of claim 13 , wherein the serial protocol comprises an Interlaken protocol.

16. The system of claim 13 , further including a bypass path to route information associated with the control words.

17. The system of claim 16 , wherein the information routed on the bypass path comprises flow control information.

18. The system of claim 16 , wherein the information routed on the bypass path comprises CRC information.

Assignments (9)
CORRECTIVE ASSIGNMENT TO CORRECT THE ERROR IN RECORDING THE MERGER IN THE INCORRECT US PATENT NO. 8,876,094 PREVIOUSLY RECORDED ON REEL 047351 FRAME 0384. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Mar 8, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 049248/0558 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE OF THE MERGER PREVIOUSLY RECORDED AT REEL: 047230 FRAME: 0910. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Oct 29, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047351/0384 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047230/0910 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: BROADCOM CORPORATION
Reel/Frame 041712/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2017
From: BROADCOM CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041706/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: BROADCOM CORPORATION
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037806/0001 →
CHANGE OF NAME Recorded Apr 16, 2015
From: NETLOGIC MICROSYSTEMS, INC.
To: NETLOGIC I LLC
Reel/Frame 035443/0824 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 16, 2015
From: NETLOGIC I LLC
To: BROADCOM CORPORATION
Reel/Frame 035443/0763 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 24, 2011
From: CHANNABASAPPA, SHANKAR
To: NETLOGIC MICROSYSTEMS, INC.
Reel/Frame 025861/0419 →