Semiconductor structure comprising pillar and moisture barrier
View Patent ↗A semiconductor structure includes multiple semiconductor devices on a substrate and a metal layer disposed over the semiconductor devices, the metal layer comprising at least a first trace and a second trace. A conductive pillar is disposed directly on and in electrical contact with the first trace of the metal layer, and a dielectric layer is selectively disposed between the metal layer and the conductive pillar, where the dielectric layer electrically isolates the second trace from the pillar. A moisture barrier surrounds the semiconductor devices around a periphery of the semiconductor structure, and extends from the substrate through the dielectric layer to the conductive pillar.
1. A semiconductor structure, comprising:
a plurality of semiconductor devices on a substrate;
a metal layer disposed over the plurality of semiconductor devices, the metal layer comprising at least a first trace and a second trace;
a conductive pillar disposed directly on and in electrical contact with the first trace of the metal layer;
a dielectric layer selectively disposed between the metal layer and the conductive pillar, wherein the dielectric layer electrically isolates the second trace from the conductive pillar; and
a moisture barrier surrounding the plurality of semiconductor devices along a periphery of the semiconductor structure, and extending from the substrate through the dielectric layer to the conductive pillar.
2. The semiconductor structure of claim 1 , wherein the moisture barrier is located between the first trace of the metal layer and an outer edge of the conductive pillar.
3. The semiconductor structure of claim 1 , wherein the moisture barrier comprises a third trace, which is formed as part of the metal layer.
4. The semiconductor structure of claim 3 , wherein the moisture barrier further comprises an insulating spacer located between the third trace and the substrate.
5. The semiconductor structure of claim 3 , wherein the moisture barrier further comprises a fourth trace, which is formed as part of another metal layer disposed between the metal layer and the plurality of semiconductor devices.
6. The semiconductor structure of claim 5 , wherein the moisture barrier further comprises an insulating spacer located between the third and fourth traces.
7. A semiconductor structure, comprising:
a semiconductor device on a substrate;
a first metal layer comprising a first trace disposed over the semiconductor device;
a second metal layer comprising second and third traces, the second trace being disposed over the first trace of the first metal layer and the third trace being separated from the first and second traces by a dielectric layer;
a moisture barrier comprising at least the third trace of the second metal layer; and a conductive pillar disposed directly on and in mechanical contact with the second trace and the third trace of the second metal layer, wherein the moisture barrier is located between the second trace of the second metal layer and an outer edge of the conductive pillar, and extends from the substrate through the dielectric layer to the conductive pillar, preventing moisture from entering the semiconductor device through the dielectric layer.
8. The semiconductor structure of claim 7 , wherein the moisture barrier surrounds the semiconductor device around a periphery of the semiconductor structure, forming a guard ring.
9. The semiconductor structure of claim 7 , wherein the guard ring includes a gap.
10. The semiconductor structure of claim 7 , wherein semiconductor device comprises a heterojunction bipolar transistor (HBT).
11. The semiconductor structure of claim 7 , wherein semiconductor device comprises a metal oxide semiconductor (MOS) device or a complementary MOS (CMOS) device.
12. The semiconductor structure of claim 7 , wherein the moisture barrier further comprises an insulating spacer formed between the substrate and the third trace of the second metal layer.
13. The semiconductor structure of claim 12 , wherein the insulating spacer comprises one of silicon nitride (Si 3 N 4 ), silicon dioxide (SiO 2 ).
14. The semiconductor structure of claim 7 , wherein the conductive pillar comprises copper.
15. The semiconductor structure of claim 14 , wherein the second metal layer comprises at least one of gold, aluminum and copper.
16. The semiconductor structure of claim 7 , wherein the first metal layer further comprises a fourth trace separated from the first trace by the dielectric layer, and
wherein the moisture barrier further comprises the fourth trace of the first metal layer, the third trace of the second metal layer being disposed over the fourth trace of the first metal layer.
17. The semiconductor structure of claim 16 , wherein the third trace of the second metal layer is in mechanical contact with the fourth trace of the first metal layer.
18. The semiconductor structure of claim 16 , wherein the third trace of the second metal layer is separated from the fourth trace of the first metal layer by an insulating spacer.
19. The semiconductor structure of claim 18 , wherein the insulating spacer comprises one of silicon nitride (Si 3 N 4 ) and silicon dioxide (SiO 2 ).
20. A semiconductor structure, comprising:
a metal layer disposed over a semiconductor device, the metal layer comprising at least a first trace and a second trace;
a conductive pillar disposed on and in direct electrical and mechanical contact with the first trace of the metal layer;
a dielectric layer selectively disposed between the metal layer and the conductive pillar, wherein the dielectric layer electrically isolates the second trace from the pillar; and
a moisture barrier around a periphery of the semiconductor structure, located between the first trace of the metal layer and an outer edge of the conductive pillar, and extending from a substrate of the semiconductor device through the dielectric layer to the conductive pillar.