IP Library Granted Patent US 8,683,100
Granted Patent B1
US 8,683,100 · App. 13/165,417 · Granted Mar 25, 2014

Method and apparatus for handling data flow in a multi-chip environment using an interchip interface

Inventor: Yan Wang (Los Gatos, CA)
Assignee: NetLogic Microsystems, Inc.
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Quick Facts
Patent No.
US 8,683,100
App. No.
13/165,417
Granted
Mar 25, 2014
Kind
B1
Abstract

A processing system includes an interchip interface that comprises an interchip interface module having an arbiter to allocate a dedicated time slice in every fixed number of time slices, to assign a first priority to store data item(s) from a first-type channel having a first datapath width in memory during the dedicated time slice. In the remaining time slices of the fixed number of time slices, the arbiter further arbitrates among multiple channels of one or more types other than a first type, where the multiple channels correspond to at least one datapath width different from the first datapath width, and channels with wider datapath win the arbitration. The arbiter further arbitrates among two or more channels of the same type if a certain type of channel(s) wins the arbitration in a time slice. A method for implementing the same is also disclosed.

Claims (79)

1. A method performed by a processing system that comprises at least one interchip interface module, the method comprising:

assigning a first priority to a first-type communication channel in a first time slice of a set of multiple time slices based at least in part upon a criterion, the set of the multiple time slices comprising the first time slice and additional time slices;

storing a first data item from the first-type communication channel in a memory element in the interchip interface module in response to at least the first priority that is assigned to the first-type communication channel;

arbitrating among one or more communication channels of one or more types other than the first-type in each of the additional time slices;

in response to the arbitrating, storing a second data item from one of the one or more communication channels of one or more types other than the first-type in the memory element in the interchip interface module; and

repeating the assigning, the storing, and the arbitrating for one or more additional sets of multiple time slices.

2. The method of claim 1 , further comprising:

determining whether or not two or more first-type communication channels are eligible for arbitration during the first time slice of the set of multiple time slices; and

performing scheduling discipline among the two or more first-type communication channels, where the two or more first-type communication channels are determined to be eligible for arbitration.

3. The method of claim 1 , wherein:

the criterion comprises a result of determining whether the first-type communication channel is eligible for arbitration.

4. The method of claim 3 , wherein, when the first-type communication channel is eligible for arbitration, assigning the first priority to the first-type communication channel in the first time slice comprises:

assigning a first weight to the first-type communication channel; and

updating a first register for the first-type communication channel based at least in part upon the first weight.

5. The method of claim 3 , wherein, when the first-type communication channel is ineligible for arbitration in the first time slice, assigning the first priority to the first-type communication channel in the first time slice comprises:

determining whether one or more second-type communication channels are eligible for arbitration during the first time slice;

arbitrating among the one or more second-type communication channels;

storing a second data item from a second-type communication channel of the one or more second-type communication channels in the memory element in the first time slice;

identifying a second time slice of the additional time slices; and

assigning first priority to the first-type communication channel in the second time slice.

6. The method of claim 3 , wherein, when the first-type communication channel and a second-type communication channel are ineligible for arbitration in the first time slice, assigning the first priority to the first-type communication channel in the first time slice comprises:

determining whether one or more third-type communication channels are eligible for arbitration;

arbitrating among the one or more third-type communication channels;

storing a third data item from a third-type communication channel of the one or more third-type communication channels in the memory element in the first time slice;

identifying a second time slice of the additional time slices; and

assigning first priority to the first-type communication channel in the second time slice

7. The method of claim 1 , wherein storing the first data item from the first-type communication channel in the memory element comprises:

identifying a contiguous memory area in the memory element;

storing the first data item into the contiguous memory area starting at a lowest memory address of the contiguous memory area; and

identifying one or more communication channels comprising one or more data items that fit a remaining portion of the memory element.

8. The method of claim 1 , wherein arbitrating among one or more communication channels other tha the first-type communication channel in each of the additional time slices comprises:

determining whether one or more second-type communication channels are eligible for arbitration in the second time slice;

determining whether one or more third-type communication channels are eligible for arbitration in the second time slice; and

determining whether one or more first-type communication channels are eligible for arbitration, when the one or more second-type communication channels and the one or more third-type communication channels are ineligible for arbitration.

9. The method of claim 8 , wherein determining whether the second-type communication channel is eligible for arbitration in the second time slice comprises:

determining whether the one or more second-type communication channels comprise more than one second-type communication channel;

assigning a second priority to a second-type communication channel of the one or more second-type communication channels based on scheduling discipline; and

storing a second data item in the memory element, when at least one of: the one or more third-type communication channels is determined to be eligible for arbitration, and the second-type communication channel is determined to be eligible for arbitration.

10. The method of claim 9 , wherein determining whether the second-type communication channel is eligible for arbitration in the second time slice comprises:

incrementing one or more counters for the one or more third-type communication channels.

11. The method of claim 9 , wherein storing the second data item in the memory element comprises:

writing the second data item in the memory element starting at a lowest memory address of the memory element.

12. The method of claim 8 , wherein determining whether the one or more second-type communication channels are eligible for arbitration in the second time slice comprises:

determining whether the one or more third-type communication channels comprise more than one third-type communication channel;

assigning a third priority to a third-type communication channel of the one or more third-type communication channels based on scheduling discipline; and

storing a third data item from the third-type communication channel in the memory element.

13. The method of claim 1 , further comprising at least one of:

transmitting, by the at least one interchip interface module, one or more data items from the processing system to another processing system; and

receiving, by the at least one interchip interface module, one or more other data items at the processing system from the another processing system.

14. A processing system, comprising:

an interchip interface module comprising:

an arbitration module configured to assign a first priority to a first-type communication channel in a first time slice of a set of multiple time slices based at least in part upon a criterion, the set of the multiple time slices comprising the first time slice and additional time slices, and to arbitrate among one or more communication channels other than the first-type communication channel in each of the additional time slices;

a memory element configured to store a first data item from the first-type communication channel in a memory element in response to at least the first priority assigned to the first-type communication channel and another data item from the one or more communication channels other than the first-type communication channel in response to the arbitrating; and

logic configured to assign the first priority, to store one or more data items from the first communication channel, and to arbitrate among one or more communication channels for one or more additional sets of the multiple time slices.

15. The processing system of claim 14 , wherein:

the arbitration module is configured to determine whether the first-type communication channel is eligible for arbitration to assign the first priority.

16. The processing system of claim 15 , wherein, when the first-type communication channel is eligible for arbitration, the arbitration module is configured to:

assign a first weight to the first-type communication channel, and

update a first register for the first-type communication channel based at least in part upon the first weight.

17. The processing system of claim 15 , wherein, when the first-type communication channel is ineligible for arbitration in the first time slice, the arbitration module is configured to:

determine whether one or more second-type communication channels are eligible for arbitration; arbitrate among the one or more second-type communication channels;

store a second data item from a second-type communication channel of the one or more second-type communication channels in the memory element in the first time slice;

identify a second time slice of the additional time slices; and

assign the first priority to the first-type communication channel in the second time slice.

18. The processing system of claim 15 , wherein, when the first-type communication channel and a second-type communication channel are ineligible for arbitration in the first time slice, the arbitration module is configured to:

determine whether one or more third-type communication channels are eligible for arbitration;

arbitrate among the one or more third-type communication channels;

store a third data item from a third-type communication channel of the one or more third-type communication channels in the memory element in the first time slice;

identify a second time slice of the one or more second time slices; and

assign first priority to the first-type communication channel in the second time slice.

19. The processing system of claim 14 , wherein the arbitration module is configured to:

determine whether one or more second-type communication channels are eligible for arbitration in the second time slice;

determine whether one or more third type communication channels are eligible for arbitration in the second time slice; and

determine whether one or more first-type communication channels are eligible for arbitration when the one or more second-type communication channels and the one or more third-type communication channels are ineligible for arbitration.

20. The processing system of claim 19 , wherein:

the first-type communication channel comprises a 144-bit datapath width;

the second-type communication channel comprises a 64-bit datapath width;

the third-type communication channel comprises a 32-bit datapath width; and

the memory includes at least five memory banks, each of which comprise a 32-bit datapath width.

Assignments (6)
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: BROADCOM CORPORATION
Reel/Frame 041712/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2017
From: BROADCOM CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041706/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: BROADCOM CORPORATION
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037806/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 16, 2015
From: NETLOGIC I LLC
To: BROADCOM CORPORATION
Reel/Frame 035443/0763 →
CHANGE OF NAME Recorded Apr 16, 2015
From: NETLOGIC MICROSYSTEMS, INC.
To: NETLOGIC I LLC
Reel/Frame 035443/0824 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 19, 2011
From: WANG, YAN
To: NETLOGIC MICROSYSTEMS, INC.
Reel/Frame 026780/0731 →