Semiconductor Device with DRAM Word Lines and Gate Electrodes in Non-Memory Regions of the Device Comprised of a Metal, and Methods of Making Same
Generally, the present disclosure is directed to a semiconductor device with DRAM word lines and gate electrodes in a non-memory region of the device made of at least one layer of metal, and various methods of making such devices. One illustrative method disclosed herein involves forming a sacrificial gate electrode structure in a logic region of the device and a word line in a memory array of the device, wherein the sacrificial gate electrode structure and the word line have a first layer of insulating material and at least one first layer comprising a metal, removing the sacrificial gate electrode structure in the logic region to define a gate opening and forming a final gate electrode structure in the gate opening.
1 . A method of forming a semiconductor device comprising a memory array and a logic region, comprising:
forming a sacrificial gate electrode structure in said logic region and a word line in said memory array, each of said sacrificial gate electrode structure and said word line comprising a first layer of insulating material and at least one first layer comprising a metal;
removing said sacrificial gate electrode structure in said logic region to define a gate opening; and
forming a final gate electrode structure in said gate opening.
2 . The method of claim 1 , wherein removing said sacrificial gate electrode structure comprises performing at least one etching process to remove said sacrificial gate electrode structure.
3 . The method of claim 1 , wherein forming said final gate electrode structure in said gate opening comprises performing a conformal deposition process to deposit a second layer of insulating material in said gate opening and performing a conformal deposition process to deposit at least one second layer comprising a metal on said second layer of insulating material.
4 . The method of claim 1 , wherein forming said sacrificial gate electrode structure in said logic region and said word line in said memory array comprises:
blanket-depositing said first layer of insulating material;
blanket-depositing said at least one first layer comprising a metal on said first layer of insulating material;
forming a patterned mask layer above said at least one first layer comprised of metal; and
performing at least one etching process on said at least one first layer comprising a metal and said first layer of insulating material through said mask layer to define said sacrificial gate electrode structure and said word line.
5 . The method of claim 4 , wherein said first layer of insulating material and said second layer of insulating material are each comprised of a high-k insulating material.
6 . The method of claim 3 , wherein said first layer of insulating material and said second layer of insulating material are each comprised of the same material.
7 . The method of claim 3 , wherein said first layer comprising a metal and said second layer comprising a metal are each comprised of the same metal or metal compound.
8 . The method of claim 3 , wherein said first layer comprising a metal and said second layer comprising a metal are each comprised of different metals or metal compounds.
9 . The method of claim 1 , further comprising forming at least one self-aligned contact between said word line and a doped region in a semiconducting substrate positioned below said word line.
10 . A method of forming a semiconductor device comprising a memory array and a logic region, comprising:
forming a sacrificial gate electrode structure in said logic region and a word line in said memory array, each of said sacrificial gate electrode structure and said word line comprising a first layer of insulating material and at least one first layer comprising a metal, by:
blanket-depositing said first layer of insulating material;
blanket-depositing said at least one first layer comprising a metal on said first layer of insulating material;
forming a patterned mask layer above said at least one first layer comprised of metal; and
performing at least one etching process on said at least one first layer comprising a metal and said first layer of insulating material through said mask layer to define said sacrificial gate electrode structure and said word line;
removing said sacrificial gate electrode structure in said logic region to define a gate opening; and
forming a final gate electrode structure in said gate opening by:
performing a conformal deposition process to deposit a second layer of insulating material in said gate opening; and
performing a conformal deposition process to deposit at least one second layer comprising a metal on said second layer of insulating material.
11 . The method of claim 10 , wherein said first layer comprising a metal and said second layer comprising a metal are each comprised of the same metal or metal compound.
12 . The method of claim 11 , wherein said first layer of insulating material and said second layer of insulating material are each comprised of the same material.
13 . The method of claim 10 , further comprising forming at least one self-aligned contact between said word line and a doped region in a semiconducting substrate positioned below said word line.
14 . A device comprising a memory array and a logic region, the device comprising:
a word line in said memory array, said word line comprising a first layer of insulating material and at least one first layer comprising a metal;
a replacement gate electrode structure in said logic region, said replacement gate electrode structure comprising a conformally deposited second layer of insulating material and a conformally deposited second layer comprising a metal positioned on said second layer of insulating material.
15 . The device of claim 14 , wherein said first layer comprising a metal and said second layer comprising a metal are comprised of the same material.
16 . The device of claim 14 , wherein said first layer comprising a metal and said second layer comprising a metal are comprised of different materials.
17 . The device of claim 14 , wherein both of said first and second layers of insulating material are comprised of a high-k insulating material.
18 . The device of claim 14 , further comprising at least one self-aligned contact between said word line and a doped region in a semiconducting substrate positioned below said word line.
19 . A device comprising a memory array and a logic region, the device comprising:
a word line in said memory array, said word line comprising a first substantially planar layer of insulating material and at least one first substantially planar layer comprising a metal;
a replacement gate electrode structure in said logic region, said replacement gate electrode structure comprising a substantially U-shaped layer of insulating material and a substantially U-shaped second layer comprising a metal positioned on said substantially U-shaped of insulating material.
20 . The device of claim 19 , further comprising at least one self-aligned contact between said word line and a doped region in a semiconducting substrate positioned below said word line.