P-I-N diode crystallized adjacent to a silicide in series with a dielectric material

1. A semiconductor device comprising:

a vertically oriented p-i-n diode comprising semiconductor material crystallized adjacent a silicide, germanide, or silicide-germanide layer; and

a dielectric material arranged electrically in series with the diode, wherein the dielectric material has a dielectric constant greater than 8, and is adjacent a first metallic layer and a second metallic layer.

2. The semiconductor device of claim 1 , wherein the dielectric material is selected from the group consisting of HfO 2 , Al 2 O 3 , ZrO 2 , TiO 2 , La 2 O 3 , Ta 2 O 5 , RuO 2 , ZrSiO x , AlSiO x , HfSiO x , HfAlO x , HfSiON, ZrSiAlO x , HfSiAlO x , HfSiAlON, and ZrSiAlON.

3. The semiconductor device of claim 1 , wherein the dielectric material is about 30 to 80 angstroms thick.

4. The semiconductor device of claim 1 , wherein the silicide, silicide-germanide, or germanide layer is a) titanium silicide, titanium silicide-germanide, or titanium germanide, or b) cobalt silicide, cobalt silicide-germanide, or cobalt germanide.

5. The semiconductor device of claim 1 , wherein the semiconductor material comprises silicon, germanium, and/or a silicon-germanium alloy.

6. The semiconductor device of claim 1 , wherein the silicide, silicide-germanide, or germanide layer is above the p-i-n diode and the dielectric material is below the p-i-n diode.

7. A first memory level comprising:

a plurality of first substantially parallel, substantially coplanar conductors formed above a substrate;

a plurality of second substantially parallel, substantially coplanar conductors formed above the first conductors;

a plurality of vertically oriented p-i-n diodes comprising semiconductor material, the semiconductor material crystallized adjacent a silicide, silicide-germanide, or germanide layer;

a plurality of dielectric material layers having a dielectric constant greater than about 8, and

a plurality of memory cells, each memory cell comprising one of the p-i-n diodes and one of the dielectric material layers,

wherein:

each of the p-i-n diodes is disposed between one of the first conductors and one of the second conductors,

each dielectric material layer is disposed between one of the first conductors and one of the p-i-n diodes or between one of the second conductors and one of the p-i-n diodes, and

each dielectric material layer is adjacent a first metallic layer and a second metallic layer.

8. The first memory level of claim 7 , wherein the dielectric material layers are selected from the group consisting of HfO 2 , Al 2 O 3 , ZrO 2 , TiO 2 , La 2 O 3 , Ta 2 O 5 , RuO 2 , ZrSiOx, AlSiO x , HfSiO x , HfAlO x , HfSiON, ZrSiAlO x , HfSiAlO x , HfSiAlON, and ZrSiAlON.

9. The first memory level of claim 7 , wherein the dielectric material layer are each about 30 to 80 angstroms thick.

10. The first memory level of claim 7 , wherein the silicide, silicide-germanide, or germanide layers are a) titanium silicide, titanium silicide-germanide, or titanium germanide, or b) cobalt silicide, cobalt silicide-germanide, or cobalt germanide.

11. The first memory level of claim 7 , wherein the semiconductor material comprises silicon, germanium, and/or a silicon-germanium alloy.

12. The first memory level of claim 7 , wherein at least a second memory level is monolithically formed above the first memory level.

13. A monolithic three dimensional memory array formed above a substrate, the array comprising:

a) a first memory level monolithically formed above the substrate, the first memory level comprising:

i) a plurality of first substantially parallel, substantially coplanar conductors extending in a first direction;

ii) a plurality of second substantially parallel, substantially coplanar conductors extending in a second direction different from the first direction, the second conductors above the first conductors;

iii) a plurality of vertically oriented p-i-n diodes formed of deposited semiconductor material, the semiconductor material crystallized adjacent to a silicide, silicide-germanide, or germanide layer, each diode vertically disposed between one of the first conductors and one of the second conductors;

iv) a plurality of dielectric material layers having a dielectric constant greater than 8, wherein each dielectric material layer is adjacent a first metallic layer and a second metallic layer; and

v) a plurality of memory cells, each memory cell comprising one of the diodes and one of the dielectric material layers arranged in series; and

b) a second memory level monolithically formed above the first memory level.

14. The monolithic three dimensional memory array of claim 13 , wherein the dielectric material is selected from the group consisting of HfO 2 , Al 2 O 3 , ZrO 2 , TiO 2 , La 2 O 3 , Ta 2 O 5 , RuO 2 , ZrSiO x , AlSiO x , HfSiO x , HfAlO x , HfSiON, ZrSiAlO x , HfSiAlO x , HfSiAlON, and ZrSiAlON.

15. The monolithic three dimensional memory array of claim 13 , wherein the dielectric material layers are less than about 50 angstroms thick.

16. The monolithic three dimensional memory array of claim 13 , wherein the dielectric material layer are about 30 to 80 angstroms thick.

17. The monolithic three dimensional memory array of claim 13 , wherein the silicide, silicide-germanide, or germanide layers are a) titanium silicide, titanium silicide-germanide, or titanium germanide, or b) cobalt silicide, cobalt silicide-germanide, or cobalt germanide.

18. The monolithic three dimensional memory array of claim 13 , wherein the semiconductor material comprises silicon, germanium, and/or a silicon-germanium alloy.