Semiconductor device
A semiconductor device includes a substrate having external connection terminals, and a semiconductor chip mounted over a semiconductor-chip mounting portion of the substrate. The external connection terminals are formed by sequentially forming an electroless nickel plating layer, an electroless gold plating layer, and an electrolytic gold plating layer on a terminal portion formed on a surface of the substrate.
1. A semiconductor device, comprising:
a substrate having a first surface, a second surface opposite to the first surface, a first external connection terminal, at least two second external connection terminals, and a first wiring pattern, the first external connection terminal and the at least two second external connection terminals being disposed on the first surface, the first surface including a chip area in a middle portion of the first surface and a peripheral area surrounding the chip area, and the chip area and the peripheral area not overlapping with one another; and
a semiconductor chip disposed on the chip area of the first surface, wherein:
the first external connection terminal is formed in the peripheral area,
the at least two second external connection terminals are formed in the peripheral area outside the first external connection terminal,
the first wiring pattern extends from the first external connection terminal to an outer periphery of the first surface,
the first wiring pattern passes through a place between adjacent ones of the at least two second external connection terminals,
the semiconductor chip and the chip area sealed and the peripheral area is not sealed,
a top surface of the first external connection terminal is exposed to air, and
top surfaces of the at least two second external connection terminals are exposed to the air.
2. The semiconductor device according to claim 1 , wherein
a second wiring pattern is formed on the first surface, and
the second wiring pattern extends from each of the at least two second external connection terminals to the outer periphery of the first surface.
3. The semiconductor device according to claim 2 , wherein multiple ones of the first external connection terminal and the at least two second external connection terminals are disposed in a grid array.
4. The semiconductor device according to claim 3 , wherein a third external connection terminal is formed on the second surface.
5. The semiconductor device according to claim 4 , wherein at least two fourth external connection terminals are formed outside the third external connection terminal on the second surface.
6. The semiconductor device according to claim 5 , wherein
a third wiring pattern extends from the third external connection terminal to an outer periphery of the second surface, and
the third wiring pattern passes through a place between adjacent ones of the at least two fourth external connection terminals.
7. The semiconductor device according to claim 6 , wherein
a fourth wiring pattern is formed on the second surface, and
the fourth wiring pattern extends from each of the at least two fourth external connection terminals to the outer periphery of the second surface.
8. The semiconductor device according to claim 7 , further comprising a plurality of chip connection terminals connected to the semiconductor chip,
wherein the plurality of chip connection terminals are disposed in the chip area.
9. The semiconductor device according to claim 8 , wherein the plurality of chip connection terminals are disposed in a grid array.
10. The semiconductor device according to claim 9 , wherein
the first external connection terminal and the at least two second external connection terminals forms a plurality of external connection terminals, and
the plurality of external connection terminals are disposed at substantially equal intervals.
11. The semiconductor device according to claim 10 , wherein a size of the first external connection terminal is larger than a size of one of the plurality of chip connection terminals.
12. The semiconductor device according to claim 11 , wherein a pitch of the plurality of chip connection terminals is narrower than a pitch of the at least two second external connection terminals.
13. The semiconductor device according to claim 12 , wherein the first wiring pattern and the second wiring pattern are covered with a solder resist.
14. The semiconductor device according to claim 13 , wherein the first wiring pattern is a Cu wiring pattern.
15. The semiconductor device according to claim 14 , wherein the second wiring pattern is a Cu wiring pattern.
16. The semiconductor device according to claim 15 , wherein the third wiring pattern is a Cu wiring pattern.
17. The semiconductor device according to claim 16 , wherein the fourth wiring pattern is a Cu wiring pattern.
18. The semiconductor device according to claim 17 , wherein the first wiring pattern is an electroplating wiring pattern.
19. The semiconductor device according to claim 18 , wherein the second wiring pattern is an electroplating wiring pattern.
20. The semiconductor device according to claim 19 , wherein the third wiring pattern is an electroplating wiring pattern.
21. The semiconductor device according to claim 20 , wherein the fourth wiring pattern is an electroplating wiring pattern.
22. The semiconductor device according to claim 1 , wherein
the substrate has a first layer and a second layer disposed on the first layer,
a first via is disposed in the first layer,
a second via is disposed in the second layer, and
the first via and the second via are electrically connected to the first external connection terminal.
23. The semiconductor device according to claim 22 , wherein the first via is disposed closer to the semiconductor chip than the second via.
24. The semiconductor device according to claim 23 , wherein
a third via is disposed in the first layer,
a fourth via is disposed in the second layer, and
the third via and the fourth via are electrically connected to one of the at least two second external connection terminals.
25. The semiconductor device according to claim 24 , wherein the third via is disposed closer to the semiconductor chip than the fourth via.
26. The semiconductor device according to claim 8 , wherein
the plurality of chip connection terminals are separated, on the first surface, from the first external connection terminal and the at least two second external connection terminals.
27. The semiconductor device according to claim 1 , wherein
a bottom face of the semiconductor chip and at least a part of a side face are sealed.
28. A semiconductor device, comprising:
a substrate having a first surface, a second surface opposite to the first surface, a first external connection terminal, at least two second external connection terminals, and a first wiring pattern, the first external connection terminal and the at least two second external connection terminals being disposed on the first surface, the first surface including a chip area in a middle portion of the first surface and a peripheral area surrounding the chip area, and the chip area and the peripheral area not overlapping with one another; and
a semiconductor chip disposed on the chip area of the first surface, wherein:
the first external connection terminal is formed in the peripheral area,
the at least two second external connection terminals are formed in the peripheral area outside the first external connection terminal,
the first wiring pattern extends from the first external connection terminal to an outer periphery of the first surface,
the first wiring pattern passes through a place between adjacent ones of the at least two second external connection terminals,
the semiconductor chip and the chip area sealed and the peripheral area is not sealed,
a top surface of the first external connection terminal is exposed,
top surfaces of the at least two second external connection terminals are exposed, and
the semiconductor chip is electrically isolated, on or above the first surface, from the first external connection terminal and the at least two second external connection terminals.
29. A semiconductor device, comprising:
a substrate having a first surface, a second surface opposite to the first surface, a first external connection terminal, at least two second external connection terminals, and a first wiring pattern, the first external connection terminal and the at least two second external connection terminals being disposed on the first surface, the first surface including a chip area in a middle portion of the first surface and a peripheral area surrounding the chip area, and the chip area and the peripheral area not overlapping with one another; and
a semiconductor chip disposed on the chip area of the first surface, wherein:
the first external connection terminal is formed in the peripheral area,
the at least two second external connection terminals are formed in the peripheral area outside the first external connection terminal,
the first wiring pattern extends from the first external connection terminal to an outer periphery of the first surface,
the first wiring pattern passes through a place between adjacent ones of the at least two second external connection terminals,
the semiconductor chip and the chip area sealed and the peripheral area is not sealed,
a top surface of the first external connection terminal is exposed,
top surfaces of the at least two second external connection terminals are exposed, and
the semiconductor chip includes a connection electrode for connecting the semiconductor chip to outside only on a bottom face of the semiconductor chip.
30. A semiconductor device, comprising:
a substrate having a first surface, a second surface opposite to the first surface, a first external connection terminal, at least two second external connection terminals, and a first wiring pattern, the first external connection terminal and the at least two second external connection terminals being disposed on the first surface, the first surface including a chip area in a middle portion of the first surface and a peripheral area surrounding the chip area, and the chip area and the peripheral area not overlapping with one another; and
a semiconductor chip disposed on the chip area of the first surface; and
a sealing material sealing the semiconductor chip and the chip area, the sealing material not sealing the peripheral area, wherein:
the first external connection terminal is formed in the peripheral area,
the at least two second external connection terminals are formed in the peripheral area outside the first external connection terminal,
the first wiring pattern extends from the first external connection terminal to an outer periphery of the first surface,
the first wiring pattern passes through a place between adjacent ones of the at least two second external connection terminals,
a top surface of the first external connection terminal is exposed to air, and
top surfaces of the at least two second external connection terminals are exposed to the air.