Systems and methods for utilizing an extended translation look-aside buffer having a hybrid memory structure
View Patent ↗Extended translation look-aside buffers (eTLB) for converting virtual addresses into physical addresses are presented, the eTLB including, a physical memory address storage having a number of physical addresses, a virtual memory address storage configured to store a number of virtual memory addresses corresponding with the physical addresses, the virtual memory address storage including, a set associative memory structure (SAM), and a content addressable memory (CAM) structure; and comparison circuitry for determining whether a requested address is present in the virtual memory address storage, wherein the eTLB is configured to receive an index register for identifying the SAM structure and the CAM structure, and wherein the eTLB is configured to receive an entry register for providing a virtual page number corresponding with the plurality of virtual memory addresses.
1. An extended Translation Lookaside Buffer (eTLB), comprising:
a plurality of set associative memories (SAMs);
a content addressable memory (CAM);
an index register configured to store an eTLB bit that indicates whether the eTLB is configured to write data to both the plurality of SAMs and the CAM; and
circuitry coupled to the SAMs, the CAM, and the index register, and configured to write data to the CAM or to write data to a SAM from the plurality of SAMs based on a page size of the data and the eTLB bit.
2. The eTLB of claim 1 , wherein the circuitry is configured to write non-protected data of a pre-determined size into a SAM from the plurality of SAMs if the eTLB bit is enabled and write all other data into the CAM.
3. The eTLB of claim 1 , further comprising an entry register that maps page sizes to SAMs, and wherein the circuitry is configured to select a SAM from the plurality of SAMs based on the mapping in the entry register.
4. The eTLB of claim 3 , wherein the circuitry is configured to select an index into the selected SAM based on virtual address bits stored in the index register.
5. The eTLB of claim 4 , wherein if an entry is to be randomly replaced in the selected SAM, the circuitry is configured to select a random way in the selected SAM.
6. The eTLB of claim 4 , wherein if an entry is not to be randomly replaced in the selected SAM, the circuitry is configured to select a way in the SAM based on a least recently used (LRU) or a not recently used (NRU) selection.
7. The eTLB of claim 1 , wherein the circuitry is configured to write the data into the CAM if the eTLB bit is disabled.
8. The eTLB of claim 7 , wherein the index register includes a structure identification bit, and wherein if the structure identification bit indicates the CAM, the circuitry is configured to select a random entry in the CAM that is not protected memory.
9. The eTLB of claim 8 , wherein the circuitry is configured to write attributes of the data including at least one of a physical page number or a frame number from the index register into the selected random entry in the CAM.
10. The eTLB of claim 1 , wherein the plurality of SAMs are configured with a fixed page size.
11. The eTLB of claim 1 , wherein the CAM is configured with a variable page size.
12. A method to select a memory in an extended Translation Lookaside Buffer (eTLB), the method comprising:
determining whether an eTLB bit stored in an index register of the eTLB is enabled, wherein the eTLB bit indicates whether the eTLB is configured to write data to both a content addressable memory (CAM) or a set associate memory (SAM) from a plurality of SAMs;
determining a page size of the data to be written; and
writing the data to the CAM or to a SAM from the plurality of SAMs based on the page size of the data and the eTLB bit.
13. The method of claim 12 , further comprising: writing non-protected data of a pre-determined size into a SAM from the plurality of SAMs if the eTLB bit is enabled and writing all other data into the CAM.
14. The method of claim 12 , further comprising: selecting a SAM from the plurality of SAMs based on a mapping of page sizes to SAMs.
15. The method of claim 14 , further comprising: selecting an index into the selected SAM based on virtual address bits stored in an index register of the eTLB.
16. The method of claim 15 , wherein the selecting step further comprises: selecting a random way in the selected SAM if an entry is to be randomly replaced in the selected SAM.
17. The method of claim 15 , wherein the selecting step further comprises: selecting a way in the selected SAM based on a least recently used (LRU) or a not recently used (MU) selection if an entry is not to be randomly replaced in the selected SAM.
18. The method of claim 12 , further comprising: writing the data into the CAM if the eTLB bit is disabled.
19. The method of claim 18 , further comprising: selecting a random entry in the CAM that is not protected memory if a structure identification bit in an index register of the eTLB indicates the CAM for writing data.
20. The method of claim 18 , further comprising writing attributes of the data including at least one of physical page number or frame number into the selected random entry in the CAM.