Content addressable memory array having local interconnects
A CAM device is disclosed that includes an array of CAM cells in which the compare circuits of groups of CAM cells are connected together using a conductive layer interposed between a polysilicon layer of the CAM device and the metal- 1 layer of the CAM device. This allows the data lines (e.g., the bit lines and/or comparand lines) of the CAM array to be formed in the metal- 1 layer of the CAM device, which in turn allows the match lines of the CAM array to be formed in the metal- 2 layer of the CAM device. The conductive layer, which may be a silicide layer, is connected to the match line by a via extending from the conductive layer through the metal- 1 layer to the metal- 2 layer.
1. A content addressable memory (CAM) device including an array of
CAM cells arranged in a number of rows and columns, wherein a respective row comprises:
a match line;
a first CAM cell coupled to the match line and including a first compare circuit; and
a second CAM cell coupled to the match line and including a second compare circuit, wherein outputs of the first and second compare circuits are connected together by an interconnect formed in a conductive layer interposed between a polysilicon layer of the CAM device and a metal- 1 layer of the CAM device.
2. The CAM device of claim 1 , wherein the conductive layer comprises silicide.
3. The CAM device of claim 1 , wherein the interconnect does not extend beyond a diffusion region within which the first and second compare circuits are formed.
4. The CAM device of claim 1 , wherein the match line is formed in a metal- 2 layer of the CAM device.
5. The CAM device of claim 4 , wherein the interconnect is connected to the match line by a via extending from the conductive layer through the metal- 1 layer to the metal- 2 layer.
6. The CAM device of claim 1 , further comprising:
a first comparand line to provide a first comparand bit to the first CAM cell during a compare operation; and
a second comparand line to provide a second comparand bit to the second CAM cell during the compare operation, wherein the first and second comparand lines are formed in the metal- 1 layer.
7. The CAM device of claim 1 , further comprising:
a first bit line to provide a first data bit for storage in the first CAM cell; and
a second bit line to provide a second data bit for storage in the second CAM cell, wherein the first and second bit lines are formed in the metal- 1 layer.
8. The CAM device of claim 1 , wherein the first and second CAM cells are adjacent to each other.
9. The CAM device of claim 1 , wherein;
the first compare circuit includes first and second pull-down transistors connected in series between the interconnect and ground potential; and
the second compare circuit includes third and fourth pull-down transistors connected in series between the interconnect and ground potential, and wherein each of the pull-down transistors has a gate comprising a terminal formed in the polysilicon layer.
10. A content addressable memory (CAM) device including an array having at least one row comprising:
a match line; and
a number of pairs of adjacent CAM cells coupled to the match line, wherein a respective pair of adjacent CAM cells comprises:
a first storage element to store a first data value;
a first compare circuit coupled to the first storage element and to a first comparand line;
a second storage element to store a second data value; and
a second compare circuit coupled to the second storage element and to a second comparand
wherein the first and second comparand lines are formed in a metal- 1 layer of the CAM device.
11. The CAM device of claim 10 , wherein the match line is formed in a metal- 2 layer of the CAM device.
12. The CAM device of claim 10 , further comprising:
an interconnect connected between outputs of the first and second compare circuits and formed in a conductive layer interposed between a polysilicon layer of the CAM device and the metal- 1 layer.
13. The CAM device of claim 12 , wherein the conductive layer comprises silicide.
14. The CAM device of claim 12 , wherein the match line is formed in a metal- 2 layer of the CAM device, and wherein the interconnect is connected to the match line by a via extending from the conductive layer through the metal- 1 layer to the metal- 2 layer.
15. The CAM device of claim 12 , wherein the interconnect does not extend beyond a diffusion region within which the first and second compare circuits are formed.
16. The CAM device of claim 10 , wherein the first compare circuit comprises:
first and second pull-down transistors, connected in series between the interconnect and ground potential, having gates comprising terminals formed in the polysilicon layer.
17. The CAM device of claim 10 , further comprising:
a first bit line to provide a first data bit for storage in the first storage element;
a second bit line to provide a second data bit for storage in the second storage element, wherein the first and second bit lines are formed in the metal- 1 layer.
18. A content addressable memory (CAM) device including an array having at least one row comprising:
a first CAM cell comprising:
a first storage cell to store a first data value; and
a first compare circuit coupled to the first storage cell and to a first comparand line;
a second CAM cell comprising:
a second storage cell to store a second data value; and
a second compare circuit coupled to the second storage cell and to a second comparand line; and
an interconnect connected between outputs of the first and second compare circuits, wherein the first and second comparand lines are formed in a metal- 1 layer of the CAM device,
and the interconnect is formed in a conductive layer interposed between a polysilicon layer of the CAM device and the metal- 1 layer.
19. The CAM device of claim 18 , wherein the conductive layer comprises silicide.
20. The CAM device of claim 18 , wherein the interconnect does not extend beyond a diffusion region within which the first and second compare circuits are formed.
21. The CAM device of claim 18 , further comprising:
a match line extending across the at least one row and coupled to the first and second CAM cells, wherein the match line is formed in a metal- 2 layer of the CAM device.
22. The CAM device of claim 18 , wherein the interconnect is connected to the match line by a via extending from the conductive layer through the metal- 1 layer to the metal- 2 layer.
23. The CAM device of claim 18 , further comprising:
a first bit line to provide a first data bit for storage in the first CAM cell; and
a second bit line to provide a second data bit for storage in the second CAM cell, wherein the first and second hit lines are formed in the metal- 1 layer.
24. The CAM device of claim 18 , wherein the first and second CAM cells are adjacent to each other.
25. The CAM device of claim 18 , wherein:
the first compare circuit includes first and second pull-down transistors connected in series between the interconnect and ground potential; and
the second compare circuit includes third and fourth pull-down transistors connected in series between the interconnect and ground potential, and wherein each of the pull-down transistors has a gate comprising a terminal formed in the polysilicon layer.