Delay line correlator
View Patent ↗A circuit for the analog correlation of a 2.5 GHz signal to remove impairments such as echo, cross talk and intersymbol interference is described. Loop stability in a loop which generates an error signal and tap weights is achieved by providing a further delay from the taps of the delay line.
1. A method comprising:
delaying a received signal in a plurality of serial analog stages (n);
further delaying a signal tapped from stage n;
combining the further delayed signal from stage n with an analog error signal to provide an analog tap weight W n ; and
combining the delayed signal from stage n with W n .
2. The method of claim 1 , wherein the step of delaying the received signal from stage n comprises receiving a signal from stage n+a, where a is a positive integer.
3. The method of claim 1 , wherein the combining of the delayed signal from stage n with W n results in a plurality of signals X n W n .
4. The method of claim 3 , including summing the plurality of signals X n W n .
5. The method of claim 4 , including slicing a signal resulting from the summing of the plurality of signals X n W n to provide the analog error signal.
6. The method defined by claim 5 , wherein there is a loop delay in the summing, slicing and the steps for forming the X n W n and wherein the further delaying provides a delay equal to or greater than the loop delay.
7. The method of claim 5 , wherein the step of delaying the received signal from stage n comprises receiving a signal from stage n+a, where a is a positive integer.
8. The method of claim 2 , wherein the combining of the delayed signal from stage n+a with W n results in a plurality of signals X n W n .
9. The method of claim 8 , including summing the plurality of signals X n W n .
10. The method of claim 9 , including slicing a signal resulting from the summing of the plurality of signals X n W n to provide the analog error signal.
11. The method defined by claim 1 , wherein generation of W n includes integrating the signal from the first combining step.
12. An apparatus comprising:
an analog delay line having a plurality of taps at each of stages (n), a first one of the stages for receiving an input signal;
a plurality of delay circuits each coupled to a tap at a stage n of the delay line to provide a delayed signal;
a plurality of first combining circuits, each for combining an error signal with the delayed signal from one of the delay circuits to provide a plurality of tap weights W n ; and
a plurality of second combining circuits, each coupled to a stage n and coupled to receive one of the weighting signals W n .
13. The apparatus of claim 12 , wherein each stage of the delay line includes an inductor and a capacitor.
14. The apparatus of claim 12 , wherein the first combining circuits each comprise a first analog multiplier.
15. The apparatus of claim 14 , including an integrator coupled to each of the first combining circuit.
16. The apparatus of claim 14 , wherein the second combining circuits each comprise a second analog multiplier.
17. The apparatus of claim 12 , including a summer coupled to the plurality of second combining circuits for summing the output of the second combining circuits.
18. The apparatus of claim 17 , including a slicer circuit coupled to receive a summed signal from the summer.
19. The apparatus of claim 18 , wherein the first combining circuits comprise first multipliers and the second combining circuits comprise second multipliers.
20. The apparatus of claim 19 , wherein each stage of the delay line comprises an inductor and capacitor.
21. An apparatus comprising:
an analog delay line having a plurality of stages (n), a first one of the stages for receiving an input signal;
a plurality of first combining circuits, each for combining an error signal with a signal tapped from one of the stages n+a of the delay line to provide a plurality of weighting signals W n , where “a” is a positive integer; and
a plurality of second combining circuits, each coupled to a stage n and coupled to receive one of the signals W n .
22. The apparatus of claim 21 , wherein each of the stages of the delay line has an inductor and a capacitor.
23. The apparatus of claim 22 , wherein each of the first combining circuits comprises a first multiplier.
24. The apparatus of claim 23 , wherein each of the second combining circuits comprise a second multiplier.
25. The apparatus of claim 24 , including a summer coupled to the second multipliers.
26. The apparatus of claim 25 , including a slicer coupled to the summer and the first multipliers.