Transmission gate-based spin-transfer torque memory unit

1. A memory unit comprising:

a magnetic tunnel junction data cell configured to switch between a high resistance state and a low resistance state by passing a polarized write current through the magnetic tunnel junction data cell; and

a NMOS transistor in parallel electrical connection with a PMOS transistor, the NMOS transistor and the PMOS transistor electrically connected with the magnetic tunnel junction data cell, the NMOS transistor and the PMOS transistor are separately addressable.

2. A memory unit according to claim 1 , wherein the NMOS transistor comprises a NMOS gate electrode electrically coupled to a first word line, and the PMOS transistor comprises a PMOS gate electrode electrically coupled to a second word line and the first word line is separately addressable from the second word line.

3. A memory unit according to claim 1 , wherein the spin-transfer torque memory unit has a symmetric driving ability for a first write current and an opposing second write current.

4. A memory unit according to claim 3 , wherein the spin-transfer torque memory unit has a symmetric driving ability for the first write current and the second write current when a voltage of 1.5V or less is applied across the spin-transfer torque memory unit.

5. A memory unit according to claim 1 , wherein the PMOS transistor is body biased.

6. A memory unit according to claim 1 , wherein the NMOS transistor comprises a NMOS gate electrode having a gate length value of 0.13 micrometer or less.

7. A memory unit according to claim 1 , wherein the NMOS transistor comprises a NMOS gate electrode having a gate length value in a range from 0.032 micrometer to 0.10 micrometer and the spin-transfer torque memory unit has a symmetric driving ability for the first write current of 1.5V or less and the second write current of −1.5V or less.

8. A spin-transfer torque memory unit comprising:

a magnetic tunnel junction data cell configured to switch between a high resistance state and a low resistance state by passing a polarized write current through the magnetic tunnel junction data cell; and

a transmission gate electrically coupled to the magnetic tunnel junction data cell, the transmission gate comprising:

a NMOS transistor in parallel electrical connection with a PMOS transistor.

9. A spin-transfer torque memory unit according to claim 8 , wherein the NMOS transistor comprises a NMOS gate electrode electrically coupled to a first word line, and the PMOS transistor comprises a PMOS gate electrode electrically coupled to a second word line and the first word line is separately addressable from the second word line.

10. A spin-transfer torque memory unit according to claim 8 , wherein the spin-transfer torque memory unit has a symmetric driving ability for a first write current and an opposing second write current.

11. A spin-transfer torque memory unit according to claim 10 , wherein the spin-transfer torque memory unit has a symmetric driving ability for the first write current and the second write current when a voltage of 1.5V or less is applied across the spin-transfer torque memory unit.

12. A spin-transfer torque memory unit according to claim 8 , wherein the PMOS transistor is body biased.

13. A spin-transfer torque memory unit according to claim 8 , wherein the NMOS transistor comprises a NMOS gate electrode having a gate length value of 0.13 micrometer or less.

14. A spin-transfer torque memory unit according to claim 13 , wherein spin-transfer torque memory unit has a symmetric driving ability for the first write current of 1.5V or less and the second write current of −1.5V or less.

15. A spin-transfer torque memory unit comprising:

a magnetic tunnel junction data cell comprising a ferromagnetic free layer and a ferromagnetic reference layer separated by a oxide barrier layer, the magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by passing a polarized write current through the magnetic tunnel junction data cell; and

a transmission gate electrically between the source line and the magnetic tunnel junction data cell, the transmission gate comprising:

a NMOS transistor in parallel electrical connection with a PMOS transistor;

a first word line is electrically coupled to the NMOS transistor; and

a second word line is electrically coupled to the PMOS transistor, the second word line being electrically isolated from the first word line;

wherein, the spin-transfer torque memory unit is configured so that a first write current in a first direction flows through the PMOS transistor and not the NMOS transistor and a second write current in a second direction flows through the NMOS transistor and not the PMOS transistor.

16. A spin-transfer torque memory unit according to claim 15 , wherein the spin-transfer torque memory unit has a symmetric driving ability for the first write current and the second write current.

17. A spin-transfer torque memory unit according to claim 15 , wherein the spin-transfer torque memory unit has a symmetric driving ability for the first write current and the second write current when a voltage of 1.5V or less is applied across the spin-transfer torque memory unit.

18. A spin-transfer torque memory unit according to claim 15 , wherein the PMOS transistor is body biased.

19. A spin-transfer torque memory unit according to claim 15 , wherein the NMOS transistor comprises a NMOS gate electrode having a gate length value of 0.13 micrometer or less.

20. A spin-transfer torque memory unit according to claim 19 , wherein spin-transfer torque memory unit has a symmetric driving ability for the first write current of 1.5V or less and the second write current of −1.5V or less.