IP Library › Granted Patent US 8,583,980
Granted Patent B2
US 8,583,980 · App. 13/619,380 · Granted Nov 12, 2013

Low density parity check (LDPC) code

Inventor: Michael Livshitz (Rockville, MD)
Assignee: Research In Motion Limited
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Quick Facts
Patent No.
US 8,583,980
App. No.
13/619,380
Granted
Nov 12, 2013
Kind
B2
Abstract

Example methods are disclosed for decoding low-density parity-check (LDPC) encoded data, involving applying an expanded parity check matrix to generate decoded data, wherein −1 represents an 81×81 all-zero square matrix, and any other integer, S ij , represents an 81×81 identity matrix circularly right shifted by a shift amount equal to S ij .

Claims (5122)

1. A method of decoding low-density parity-check (LDPC) encoded data, comprising:

applying the following expanded parity check matrix to generate decoded data:

61

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-

1

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1

8

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1

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1

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1

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4

67

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1

7

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1

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21

68

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7

14

65

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1

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1

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1

23

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1

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1

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1

75

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1

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1

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1

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36

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1

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2

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25

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1

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1

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1

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22

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1

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1

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0

wherein −1 represents an 81×81 all-zero square matrix, and

any other integer, S ij , represents an 81×81 identity matrix circularly right shifted by a shift amount equal to S ij .

2. A method as defined in claim 1 , wherein applying the expanded parity check matrix comprises applying the expanded parity check matrix to 1296 input bits, the decoded data comprising 648 parity bits.

3. An apparatus for encoding data using low-density parity-check (LDPC), comprising:

circuitry operable to apply the following expanded parity check matrix to generate encoded data:

61

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0

wherein −1 represents an 81×81 all-zero square matrix, and

any other integer, S i,j , represents an 81×81 identity matrix circularly right shifted by a shift amount equal to S ij .

4. The apparatus as defined in claim 3 , wherein the circuitry is to apply the expanded parity check matrix to 1296 input bits, the encoded data comprising 648 parity bits.

5. An apparatus for encoding data using low-density parity-check (LDPC), comprising:

a matrix application element operable to apply the following expanded parity check matrix to generate encoded data:

61

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1

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1

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58

1

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1

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1

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1

-

1

0

wherein −1 represents an 81×81 all-zero square matrix, and

any other integer, S ij , represents an 81×81 identity matrix circularly right shifted by a shift amount equal to S ij .

6. The apparatus as defined in claim 5 , wherein the matrix application element is to apply the expanded parity check matrix to 1296 input bits, the encoded data comprising 648 parity bits.

7. An apparatus for decoding low-density parity-check (LDPC) encoded data, comprising:

circuitry operable to apply the following expanded parity check matrix to generate decoded data:

61

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4

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1

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1

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1

-

1

-

1

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1

8

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1

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58

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1

-

1

0

wherein −1 represents an 81×81 all-zero square matrix, and

any other integer, S ij , represents an 81×81 identity matrix circularly right shifted by a shift amount equal to S ij .

8. The apparatus as defined in claim 7 , wherein the circuitry is to apply the expanded parity check matrix to 1296 input bits, the decoded data comprising 648 parity bits.

9. An apparatus for decoding low-density parity-check (LDPC) encoded data, comprising:

a matrix application element operable to apply the following expanded parity check matrix to generate decoded data:

61

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4

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1

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1

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1

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8

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52

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34

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1

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1

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1

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1

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1

58

1

-

1

-

1

-

1

-

1

-

1

-

1

0

wherein −1 represents an 81×81 all-zero square matrix, and

any other integer, S ij , represents an 81×81 identity matrix circularly right shifted by a shift amount equal to S ij .

10. The apparatus as defined in claim 9 , wherein the matrix application element is to apply the expanded parity check matrix to 1296 input bits, the decoded data comprising 648 parity bits.

11. A telecommunications network, comprising:

a low-density parity-check (LDPC) encoder operable to apply the following expanded parity check matrix to generate encoded data:

61

75

4

63

56

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1

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1

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4

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7

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1

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58

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1

-

1

0

wherein −1 represents an 81×81 all-zero square matrix, and

any other integer, S ij , represents an 81×81 identity matrix circularly right shifted by a shift amount equal to S ij ; and

an LDPC decoder operable to apply the expanded parity check matrix to recover input data.

12. A telecommunications network as defined in claim 11 , wherein the LDPC encoder is to apply the expanded parity check matrix to 1296 input bits, the encoded data comprising 648 parity bits.

13. A method of operating a telecommunications network, comprising:

applying the following expanded parity check matrix to generate encoded data:

61

75

4

63

56

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1

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1

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1

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1

-

1

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1

8

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1

2

17

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0

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74

77

20

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64

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4

67

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1

7

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7

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69

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68

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0

68

20

55

61

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1

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1

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1

52

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1

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1

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1

44

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1

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1

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1

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1

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0

58

8

34

64

78

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1

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1

11

78

24

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1

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1

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1

-

1

-

1

58

1

-

1

-

1

-

1

-

1

-

1

-

1

0

wherein −1 represents an 81×81 all-zero square matrix, and

any other integer, S ij , represents an 81×81 identity matrix circularly right shifted by a shift amount equal to S ij ; and

applying the expanded parity check matrix to recover input data.

14. A method as defined in claim 13 , wherein applying the expanded parity check matrix comprises applying the expanded parity check matrix to 1296 input bits, the encoded data comprising 648 parity bits.

15. A transceiver, comprising:

a low-density parity-check (LDPC) encoder operable to apply the following expanded parity check matrix to generate encoded data:

61

75

4

63

56

-

1

-

1

-

1

-

1

-

1

-

1

8

-

1

2

17

25

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0

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1

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56

74

77

20

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4

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7

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40

-

1

-

1

-

1

52

-

1

-

1

-

1

44

-

1

-

1

-

1

-

1

-

1

-

1

0

0

58

8

34

64

78

-

1

-

1

11

78

24

-

1

-

1

-

1

-

1

-

1

58

1

-

1

-

1

-

1

-

1

-

1

-

1

0

wherein −1 represents an 81×81 all-zero square matrix, and

any other integer, S ij , represents an 81×81 identity matrix circularly right shifted by a shift amount equal to S ij ; and

an LDPC decoder operable to apply the expanded parity check matrix to generate decoded data.

16. A transceiver as defined in claim 15 , wherein the LDPC encoder is to apply the expanded parity check matrix to 1296 input bits, the encoded data comprising 648 parity bits.

17. A method of operating a transceiver, comprising:

applying the following expanded parity check matrix to generate encoded data:

61

75

4

63

56

-

1

-

1

-

1

-

1

-

1

-

1

8

-

1

2

17

25

1

0

-

1

-

1

-

1

-

1

-

1

-

1

56

74

77

20

-

1

-

1

-

1

64

24

4

67

-

1

7

-

1

-

1

-

1

-

1

0

0

-

1

-

1

-

1

-

1

-

1

28

21

68

10

7

14

65

-

1

-

1

-

1

23

-

1

-

1

-

1

75

-

1

-

1

-

1

0

0

-

1

-

1

-

1

-

1

48

38

43

78

76

-

1

-

1

-

1

-

1

5

36

-

1

15

72

-

1

-

1

-

1

-

1

-

1

0

0

-

1

-

1

-

1

40

2

53

25

-

1

52

62

-

1

20

-

1

-

1

44

-

1

-

1

-

1

-

1

0

-

1

-

1

-

1

0

0

-

1

-

1

69

23

64

10

22

-

1

21

-

1

-

1

-

1

-

1

-

1

68

23

29

-

1

-

1

-

1

-

1

-

1

-

1

0

0

-

1

12

0

68

20

55

61

-

1

40

-

1

-

1

-

1

52

-

1

-

1

-

1

44

-

1

-

1

-

1

-

1

-

1

-

1

0

0

58

8

34

64

78

-

1

-

1

11

78

24

-

1

-

1

-

1

-

1

-

1

58

1

-

1

-

1

-

1

-

1

-

1

-

1

0

wherein −1 represents an 81×81 all-zero square matrix, and

any other integer, S ij , represents an 81×81 identity matrix circularly right shifted by a shift amount equal to S ij ; and

applying the expanded parity check matrix to generate decoded data.

18. A method as defined in claim 17 , wherein applying the expanded parity check matrix comprises applying the expanded parity check matrix to 1296 input bits, the encoded data comprising 648 parity bits.

19. A method of decoding low-density parity-check (LDPC) encoded data, comprising:

decoding the LDPC encoded data using an expanded parity check matrix:

61

75

4

63

56

-

1

-

1

-

1

-

1

-

1

-

1

8

-

1

2

17

25

1

0

-

1

-

1

-

1

-

1

-

1

-

1

56

74

77

20

-

1

-

1

-

1

64

24

4

67

-

1

7

-

1

-

1

-

1

-

1

0

0

-

1

-

1

-

1

-

1

-

1

28

21

68

10

7

14

65

-

1

-

1

-

1

23

-

1

-

1

-

1

75

-

1

-

1

-

1

0

0

-

1

-

1

-

1

-

1

48

38

43

78

76

-

1

-

1

-

1

-

1

5

36

-

1

15

72

-

1

-

1

-

1

-

1

-

1

0

0

-

1

-

1

-

1

40

2

53

25

-

1

52

62

-

1

20

-

1

-

1

44

-

1

-

1

-

1

-

1

0

-

1

-

1

-

1

0

0

-

1

-

1

69

23

64

10

22

-

1

21

-

1

-

1

-

1

-

1

-

1

68

23

29

-

1

-

1

-

1

-

1

-

1

-

1

0

0

-

1

12

0

68

20

55

61

-

1

40

-

1

-

1

-

1

52

-

1

-

1

-

1

44

-

1

-

1

-

1

-

1

-

1

-

1

0

0

58

8

34

64

78

-

1

-

1

11

78

24

-

1

-

1

-

1

-

1

-

1

58

1

-

1

-

1

-

1

-

1

-

1

-

1

0

wherein −1 represents an 81×81 all-zero square matrix, and

any other integer, S ij , represents an 81×81 identity matrix circularly right shifted by a shift amount equal to S ij .

20. The method as defined in claim 19 , wherein using the expanded parity check matrix comprises applying the expanded parity check matrix to 1296 input bits.

21. An apparatus for decoding low-density parity-check (LDPC) encoded data, comprising:

circuitry configured to decode the LDPC encoded data using the following expanded parity check matrix:

61

75

4

63

56

-

1

-

1

-

1

-

1

-

1

-

1

8

-

1

2

17

25

1

0

-

1

-

1

-

1

-

1

-

1

-

1

56

74

77

20

-

1

-

1

-

1

64

24

4

67

-

1

7

-

1

-

1

-

1

-

1

0

0

-

1

-

1

-

1

-

1

-

1

28

21

68

10

7

14

65

-

1

-

1

-

1

23

-

1

-

1

-

1

75

-

1

-

1

-

1

0

0

-

1

-

1

-

1

-

1

48

38

43

78

76

-

1

-

1

-

1

-

1

5

36

-

1

15

72

-

1

-

1

-

1

-

1

-

1

0

0

-

1

-

1

-

1

40

2

53

25

-

1

52

62

-

1

20

-

1

-

1

44

-

1

-

1

-

1

-

1

0

-

1

-

1

-

1

0

0

-

1

-

1

69

23

64

10

22

-

1

21

-

1

-

1

-

1

-

1

-

1

68

23

29

-

1

-

1

-

1

-

1

-

1

-

1

0

0

-

1

12

0

68

20

55

61

-

1

40

-

1

-

1

-

1

52

-

1

-

1

-

1

44

-

1

-

1

-

1

-

1

-

1

-

1

0

0

58

8

34

64

78

-

1

-

1

11

78

24

-

1

-

1

-

1

-

1

-

1

58

1

-

1

-

1

-

1

-

1

-

1

-

1

0

wherein −1 represents an 81×81 all-zero square matrix, and

any other integer, S ij , represents an 81×81 identity matrix circularly right shifted by a shift amount equal to S ij .

22. The apparatus as defined in claim 21 , wherein the circuitry is further configured to apply the expanded parity check matrix to 1296 input bits.

23. An apparatus for encoding data using low-density parity-check (LDPC), comprising:

circuitry configured to encode the data using the following expanded parity check matrix:

61

75

4

63

56

-

1

-

1

-

1

-

1

-

1

-

1

8

-

1

2

17

25

1

0

-

1

-

1

-

1

-

1

-

1

-

1

56

74

77

20

-

1

-

1

-

1

64

24

4

67

-

1

7

-

1

-

1

-

1

-

1

0

0

-

1

-

1

-

1

-

1

-

1

28

21

68

10

7

14

65

-

1

-

1

-

1

23

-

1

-

1

-

1

75

-

1

-

1

-

1

0

0

-

1

-

1

-

1

-

1

48

38

43

78

76

-

1

-

1

-

1

-

1

5

36

-

1

15

72

-

1

-

1

-

1

-

1

-

1

0

0

-

1

-

1

-

1

40

2

53

25

-

1

52

62

-

1

20

-

1

-

1

44

-

1

-

1

-

1

-

1

0

-

1

-

1

-

1

0

0

-

1

-

1

69

23

64

10

22

-

1

21

-

1

-

1

-

1

-

1

-

1

68

23

29

-

1

-

1

-

1

-

1

-

1

-

1

0

0

-

1

12

0

68

20

55

61

-

1

40

-

1

-

1

-

1

52

-

1

-

1

-

1

44

-

1

-

1

-

1

-

1

-

1

-

1

0

0

58

8

34

64

78

-

1

-

1

11

78

24

-

1

-

1

-

1

-

1

-

1

58

1

-

1

-

1

-

1

-

1

-

1

-

1

0

wherein −1 represents an 81×81 all-zero square matrix, and

any other integer, S ij , represents an 81×81 identity matrix circularly right shifted by a shift amount equal to S ij .

24. The apparatus as defined in claim 23 , wherein the circuitry is further configured to apply the expanded parity check matrix to 1296 input bits.

25. A method of encoding data using low-density parity-check (LDPC), comprising:

encoding the data using the following expanded parity check matrix:

61

75

4

63

56

-

1

-

1

-

1

-

1

-

1

-

1

8

-

1

2

17

25

1

0

-

1

-

1

-

1

-

1

-

1

-

1

56

74

77

20

-

1

-

1

-

1

64

24

4

67

-

1

7

-

1

-

1

-

1

-

1

0

0

-

1

-

1

-

1

-

1

-

1

28

21

68

10

7

14

65

-

1

-

1

-

1

23

-

1

-

1

-

1

75

-

1

-

1

-

1

0

0

-

1

-

1

-

1

-

1

48

38

43

78

76

-

1

-

1

-

1

-

1

5

36

-

1

15

72

-

1

-

1

-

1

-

1

-

1

0

0

-

1

-

1

-

1

40

2

53

25

-

1

52

62

-

1

20

-

1

-

1

44

-

1

-

1

-

1

-

1

0

-

1

-

1

-

1

0

0

-

1

-

1

69

23

64

10

22

-

1

21

-

1

-

1

-

1

-

1

-

1

68

23

29

-

1

-

1

-

1

-

1

-

1

-

1

0

0

-

1

12

0

68

20

55

61

-

1

40

-

1

-

1

-

1

52

-

1

-

1

-

1

44

-

1

-

1

-

1

-

1

-

1

-

1

0

0

58

8

34

64

78

-

1

-

1

11

78

24

-

1

-

1

-

1

-

1

-

1

58

1

-

1

-

1

-

1

-

1

-

1

-

1

0

wherein −1 represents an 81×81 all-zero square matrix, and

any other integer, S ij , represents an 81×81 identity matrix circularly right shifted by a shift amount equal to S ij .

26. The method as defined in claim 25 , wherein using the expanded parity check matrix comprises applying the expanded parity check matrix to 1296 input bits.

27. An apparatus for encoding data using low-density parity-check (LDPC), comprising:

a matrix application element configured to encode the data using the following expanded parity check matrix:

61

75

4

63

56

-

1

-

1

-

1

-

1

-

1

-

1

8

-

1

2

17

25

1

0

-

1

-

1

-

1

-

1

-

1

-

1

56

74

77

20

-

1

-

1

-

1

64

24

4

67

-

1

7

-

1

-

1

-

1

-

1

0

0

-

1

-

1

-

1

-

1

-

1

28

21

68

10

7

14

65

-

1

-

1

-

1

23

-

1

-

1

-

1

75

-

1

-

1

-

1

0

0

-

1

-

1

-

1

-

1

48

38

43

78

76

-

1

-

1

-

1

-

1

5

36

-

1

15

72

-

1

-

1

-

1

-

1

-

1

0

0

-

1

-

1

-

1

40

2

53

25

-

1

52

62

-

1

20

-

1

-

1

44

-

1

-

1

-

1

-

1

0

-

1

-

1

-

1

0

0

-

1

-

1

69

23

64

10

22

-

1

21

-

1

-

1

-

1

-

1

-

1

68

23

29

-

1

-

1

-

1

-

1

-

1

-

1

0

0

-

1

12

0

68

20

55

61

-

1

40

-

1

-

1

-

1

52

-

1

-

1

-

1

44

-

1

-

1

-

1

-

1

-

1

-

1

0

0

58

8

34

64

78

-

1

-

1

11

78

24

-

1

-

1

-

1

-

1

-

1

58

1

-

1

-

1

-

1

-

1

-

1

-

1

0

wherein −1 represents an 81×81 all-zero square matrix, and

any other integer, S ij , represents an 81×81 identity matrix circularly right shifted by a shift amount equal to S ij .

28. The apparatus as defined in claim 27 , wherein the matrix application element is further configured to apply the expanded parity check matrix to 1296 input bits.

29. An apparatus for decoding low-density parity-check (LDPC) encoded data, comprising:

a matrix application element configured to decode the LDPC encoded data using the following expanded parity check matrix:

61

75

4

63

56

-

1

-

1

-

1

-

1

-

1

-

1

8

-

1

2

17

25

1

0

-

1

-

1

-

1

-

1

-

1

-

1

56

74

77

20

-

1

-

1

-

1

64

24

4

67

-

1

7

-

1

-

1

-

1

-

1

0

0

-

1

-

1

-

1

-

1

-

1

28

21

68

10

7

14

65

-

1

-

1

-

1

23

-

1

-

1

-

1

75

-

1

-

1

-

1

0

0

-

1

-

1

-

1

-

1

48

38

43

78

76

-

1

-

1

-

1

-

1

5

36

-

1

15

72

-

1

-

1

-

1

-

1

-

1

0

0

-

1

-

1

-

1

40

2

53

25

-

1

52

62

-

1

20

-

1

-

1

44

-

1

-

1

-

1

-

1

0

-

1

-

1

-

1

0

0

-

1

-

1

69

23

64

10

22

-

1

21

-

1

-

1

-

1

-

1

-

1

68

23

29

-

1

-

1

-

1

-

1

-

1

-

1

0

0

-

1

12

0

68

20

55

61

-

1

40

-

1

-

1

-

1

52

-

1

-

1

-

1

44

-

1

-

1

-

1

-

1

-

1

-

1

0

0

58

8

34

64

78

-

1

-

1

11

78

24

-

1

-

1

-

1

-

1

-

1

58

1

-

1

-

1

-

1

-

1

-

1

-

1

0

wherein −1 represents an 81×81 all-zero square matrix, and

any other integer, S ij , represents an 81×81 identity matrix circularly right shifted by a shift amount equal to S ij .

30. The apparatus as defined in claim 29 , wherein the matrix application element is further configured to apply the expanded parity check matrix to 1296 input bits.

31. A device comprising:

a low-density parity-check (LDPC) encoder configured to:

encode data using the following expanded parity check matrix:

61

75

4

63

56

-

1

-

1

-

1

-

1

-

1

-

1

8

-

1

2

17

25

1

0

-

1

-

1

-

1

-

1

-

1

-

1

56

74

77

20

-

1

-

1

-

1

64

24

4

67

-

1

7

-

1

-

1

-

1

-

1

0

0

-

1

-

1

-

1

-

1

-

1

28

21

68

10

7

14

65

-

1

-

1

-

1

23

-

1

-

1

-

1

75

-

1

-

1

-

1

0

0

-

1

-

1

-

1

-

1

48

38

43

78

76

-

1

-

1

-

1

-

1

5

36

-

1

15

72

-

1

-

1

-

1

-

1

-

1

0

0

-

1

-

1

-

1

40

2

53

25

-

1

52

62

-

1

20

-

1

-

1

44

-

1

-

1

-

1

-

1

0

-

1

-

1

-

1

0

0

-

1

-

1

69

23

64

10

22

-

1

21

-

1

-

1

-

1

-

1

-

1

68

23

29

-

1

-

1

-

1

-

1

-

1

-

1

0

0

-

1

12

0

68

20

55

61

-

1

40

-

1

-

1

-

1

52

-

1

-

1

-

1

44

-

1

-

1

-

1

-

1

-

1

-

1

0

0

58

8

34

64

78

-

1

-

1

11

78

24

-

1

-

1

-

1

-

1

-

1

58

1

-

1

-

1

-

1

-

1

-

1

-

1

0

wherein −1 represents an 81×81 all-zero square matrix, and

any other integer, S ij , represents an 81×81 identity matrix circularly right shifted by a shift amount equal to S ij .

32. A device comprising:

a low-density parity-check (LDPC) decoder configured to:

decode encoded data using an expanded parity check matrix:

61

75

4

63

56

-

1

-

1

-

1

-

1

-

1

-

1

8

-

1

2

17

25

1

0

-

1

-

1

-

1

-

1

-

1

-

1

56

74

77

20

-

1

-

1

-

1

64

24

4

67

-

1

7

-

1

-

1

-

1

-

1

0

0

-

1

-

1

-

1

-

1

-

1

28

21

68

10

7

14

65

-

1

-

1

-

1

23

-

1

-

1

-

1

75

-

1

-

1

-

1

0

0

-

1

-

1

-

1

-

1

48

38

43

78

76

-

1

-

1

-

1

-

1

5

36

-

1

15

72

-

1

-

1

-

1

-

1

-

1

0

0

-

1

-

1

-

1

40

2

53

25

-

1

52

62

-

1

20

-

1

-

1

44

-

1

-

1

-

1

-

1

0

-

1

-

1

-

1

0

0

-

1

-

1

69

23

64

10

22

-

1

21

-

1

-

1

-

1

-

1

-

1

68

23

29

-

1

-

1

-

1

-

1

-

1

-

1

0

0

-

1

12

0

68

20

55

61

-

1

40

-

1

-

1

-

1

52

-

1

-

1

-

1

44

-

1

-

1

-

1

-

1

-

1

-

1

0

0

58

8

34

64

78

-

1

-

1

11

78

24

-

1

-

1

-

1

-

1

-

1

58

1

-

1

-

1

-

1

-

1

-

1

-

1

0

wherein −1 represents an 81×81 all-zero square matrix, and

any other integer, S ij , represents an 81×81 identity matrix circularly right shifted by a shift amount equal to S ij .

Assignments (11)
CORRECTIVE ASSIGNMENT TO CORRECT THE ADDED PATENT NUMBER TO REMOVE PATENT NO. 8,873,407 AT PREVIOUSLY RECORDED ON REEL 64066 FRAME 1. ASSIGNOR(S) HEREBY CONFIRMS THE NUNC PRO TUNC ASSIGNMENT EFFECTIVE DATE MARCH 20, 2023. Recorded Feb 2, 2026
From: BLACKBERRY LIMITED
To: MALIKIE INNOVATIONS LIMITED
Reel/Frame 074921/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT 12817157 APPLICATION NUMBER PREVIOUSLY RECORDED AT REEL: 064015 FRAME: 0001. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Sep 5, 2023
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To: MALIKIE INNOVATIONS LIMITED
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CHANGE OF NAME Recorded Oct 16, 2014
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To: BLACKBERRY LIMITED
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From: LIVSHITZ, MICHAEL
To: NORTEL NETWORKS LIMITED
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Continuity (15)
Continuation 13346155 · Jan 9, 2012
Continuation 12987729 · Jan 10, 2011
Continuation 12796453 · Jun 8, 2010
Continuation 11393622 · Mar 30, 2006
Continuation In Part PCTCA2005001563 · Oct 12, 2005
Provisional Application 60727932 · Oct 18, 2005
Provisional Application 60673323 · Apr 20, 2005
Provisional Application 60656587 · Feb 25, 2005
Provisional Application 60647259 · Jan 26, 2005
Provisional Application 60639420 · Dec 27, 2004
Provisional Application 60638832 · Dec 22, 2004
Provisional Application 60635525 · Dec 13, 2004
Provisional Application 60627348 · Nov 12, 2004
Provisional Application 60617902 · Oct 12, 2004
Related Publication 20130013973A1 · Jan 10, 2013