Programmable drive strength in memory signaling
View Patent ↗Embodiments of the invention relate to programmable data register circuits and programmable clock generation circuits For example, some embodiments include a buffer circuit for receiving input data and sending output data signals along a series of signal lines with a signal strength, and a signal modulator configured to determine the signal strength based on a control input. Some embodiments include a clock generation circuit for receiving clock reference and sending output clock signals along a series of signal lines with a signal character, and a signal modulator configured to determine the signal character based on a control input.
1. A method of tuning a memory circuit, comprising:
receiving a control signal that contains data indicative of a desired output characteristic;
storing the data indicative of a desired output characteristic as a control value in a non-volatile memory;
generating an output signal based on an input signal; and
tuning the generated output signal so that it conforms to the desired output characteristic based on the control value stored in the non-volatile memory.
2. The method of claim 1 , wherein the receiving the control signal comprises:
receiving the control signal that contains the data indicative of at least one of: a current, an output impedance, and a phase.
3. The method of claim 1 , further comprising:
storing the received data in the non-volatile memory.
4. The method of claim 3 , further comprising:
retrieving the stored data from the non-volatile memory.
5. The method of claim 4 , wherein the generating comprises:
generating the output signal based on the stored data retrieved from the non-volatile memory.
6. The method of claim 1 , further comprising:
receiving a second control signal that contains second data indicative of a new desired output characteristic.
7. The method of claim 6 , further comprising:
re-tuning the generated output signal so that it conforms with the new desired output characteristic.
8. The method of claim 1 , wherein the receiving the control signal comprises:
receiving the control signal when the memory circuit boots up.
9. The method of claim 1 , further comprising:
receiving a new control signal at regular intervals while the memory circuit is operating.
10. The method of claim 1 , wherein the receiving the input signal comprises:
receiving a clock signal.
11. A circuit for use in a memory, comprising:
a control signal input configured to receive a control signal containing data indicative of a desired output characteristic;
a non-volatile memory configured to store the data indicative of the desired output characteristic;
a processor configured to generate an output signal based on a received input signal; and
a signal modulator configured to tune the generated output signal so that it conforms to the desired output characteristic.
12. The circuit of claim 11 , wherein the desired output characteristic includes at least one of: a current, an output impedance, and a phase.
13. The circuit of claim 11 , wherein the signal modulator is configured to tune the generated output signal according to the stored data retrieved from the non-volatile memory.
14. The circuit of claim 11 , wherein the non-volatile memory is further configured to store second data indicative of a new desired output characteristic.
15. The circuit of claim 14 , wherein the signal modulator is further configured to re-tune the generated output signal so that it conforms with the new desired output characteristic.
16. The circuit of claim 11 , wherein the control signal input is configured to receive the control signal when the memory boots up.
17. The circuit of claim 11 , wherein the control signal input is configured to receive a new control signal at regular intervals while the memory is operating.
18. The circuit of claim 11 , wherein the signal modulator comprises at least one of: a current modulator, an impedance matcher, and a phase controller.
19. The circuit of claim 11 , wherein the received input signal comprises a clock input signal.
20. A non-transitory computer-readable medium containing computer instructions that, when executed by a processor, cause the processor to perform steps, comprising:
receiving a control signal that contains data indicative of a desired output characteristic;
storing the data indicative of the desired output characteristic as a control value in a non-volatile memory;
generating an output signal based on an input signal; and
tuning the generated output signal so that it conforms to the desired output characteristic based on the control value stored in the non-volatile memory.