Semiconductor devices having stressor regions and related fabrication methods
View Patent ↗Apparatus for semiconductor device structures and related fabrication methods are provided. A method for fabricating a semiconductor device structure on an isolated region of semiconductor material comprises forming a plurality of gate structures overlying the isolated region of semiconductor material and masking edge portions of the isolated region of semiconductor material. While the edge portions are masked, the fabrication method continues by forming recesses between gate structures of the plurality of gate structures and forming stressor regions in the recesses. The method continues by unmasking the edge portions and implanting ions of a conductivity-determining impurity type into the stressor regions and the edge portions.
1. A semiconductor device comprising:
a region of semiconductor material having a first conductivity type;
an isolation region about the entire periphery of the region of semiconductor material, wherein the isolation region electrically insulates the region of semiconductor material;
a stressor region formed in the region of semiconductor material and comprising a first stressor region;
a first gate structure, a second gate structure, and a third gate structure formed overlying the region of semiconductor material, wherein the stressor region is disposed between the first gate structure and the second gate structure;
a second stressor region formed in the region of semiconductor material between the second gate structure and the third gate structure;
a first source/drain region having a second conductivity type formed in a first portion of the region of semiconductor material disposed between the first gate structure and the isolation region, the first source/drain region being adjacent to a channel region underlying the first gate structure; and
a second source/drain region having the second conductivity type formed in the stressor region, the second source/drain region being adjacent to the channel region underlying the first gate structure;
wherein the first gate structure, the second gate structure, and the third gate structure are in electrical communication with shared source/drain regions disposed therebetween.
2. The semiconductor device of claim 1 , wherein a second portion of the region of semiconductor material is disposed between the third gate structure and the isolation region.
3. The semiconductor device of claim 2 , further comprising:
a third source/drain region having the second conductivity type formed in the second portion, the third source/drain region being adjacent to a second channel region underlying the third gate structure; and
a fourth source/drain region having the second conductivity type formed in the second stressor region, the fourth source/drain region being adjacent to the second channel region underlying the third gate structure.
4. The semiconductor device of claim 1 , wherein adjacent edges of the first portion of the region of semiconductor material are in contact with the isolation region.
5. The semiconductor device of claim 1 , wherein the first portion of the region of semiconductor material has three edges in contact with the isolation region.
6. The semiconductor device of claim 1 , wherein:
the first portion of the region of semiconductor material comprises an unstressed portion of the region of semiconductor material disposed between the first gate structure and the isolation region; and
the first source/drain region is formed in the unstressed portion of the region of semiconductor material.
7. The semiconductor device of claim 1 , wherein each stressor region has a first set of opposing boundaries and a second set of opposing boundaries;
wherein each boundary of the first set of opposing boundaries is adjacent to a channel region underlying a respective gate structure of the plurality of gate structures; and
wherein each boundary of the second set of opposing boundaries is adjacent to the isolation region.
8. The semiconductor device of claim 1 , wherein the first gate structure is an outer gate structure adjacent to only the second gate structure and wherein the second gate structure is adjacent to the first gate structure and the third gate structure.
9. The semiconductor device of claim 8 , wherein the first gate structure is adjacent to the single stressor region disposed between the first gate structure and the second gate structure.
10. The semiconductor device of claim 9 , wherein the second gate structure has stressor regions adjacent to both sides of the second gate structure.
11. The semiconductor device of claim 8 , wherein the second source/drain region is an inner source/drain region and is contiguous with source/drain regions of the second gate structure.
12. The semiconductor device of claim 1 , wherein the first gate structure, the second gate structure, and the third gate structure comprise a multi-finger gate structure.