REPLACEMENT GATE ELECTRODE WITH A SELF-ALIGNED DIELECTRIC SPACER
A dielectric disposable gate structure can be formed across a semiconductor material portion, and active semiconductor regions are formed within the semiconductor material portion. Raised active semiconductor regions are grown over the active semiconductor regions while the dielectric disposable gate structure limits the extent of the raised active semiconductor regions. A planarization dielectric layer is formed over the raised active semiconductor regions. In one embodiment, the dielectric disposable gate structure is removed, and a dielectric gate spacer can be formed by conversion of surface portions of the raised active semiconductor regions around a gate cavity. Alternately, an etch mask layer overlying peripheral portions of the disposable gate structure can be formed, and a gate cavity and a dielectric spacer can be formed by anisotropically etching an unmasked portion of the dielectric disposable gate structure. A replacement gate structure can be formed in the gate cavity.
1 . A semiconductor structure comprising:
a semiconductor material portion including a body region, a source region, and a drain region;
a gate stack including a gate dielectric and a gate electrode, wherein said gate stack straddles said body region;
a first dielectric spacer contacting a first vertical sidewall of said gate dielectric; and
a second dielectric spacer contacting a second vertical sidewall of said gate dielectric and laterally spaced from said first dielectric spacer by said gate stack.
2 . The semiconductor structure of claim 1 , further comprising:
a raised source region contacting said source region and a sidewall of said first dielectric spacer; and
a raised drain region contacting said drain region and a sidewall of said second dielectric spacer.
3 . The semiconductor structure of claim 1 , wherein said raised source region and said raised drain region comprises a doped semiconductor material, and said first and second dielectric spacers comprise a dielectric material that is an oxide, a nitride, or an oxynitride of said doped semiconductor material.
4 . The semiconductor structure of claim 1 , further comprising a planarization dielectric layer having a top surface that is coplanar with a topmost surface of said gate stack, wherein topmost surfaces of said first and second dielectric spacers are located underneath a horizontal plane including said topmost surface of said gate stack.
5 . The semiconductor structure of claim 1 , wherein said gate electrode includes a portion having a variable horizontal cross-sectional area that increases with a vertical distance from said body region.
6 . The semiconductor structure of claim 5 , wherein said gate electrode further includes:
a lower portion that underlies said portion and having a first constant horizontal cross-sectional area that is invariant with said vertical distance; and
an upper portion that overlies said portion and having a second constant horizontal cross-sectional area that is greater than said first constant horizontal cross-sectional area and is invariant with said vertical distance.
7 . The semiconductor structure of claim 1 , wherein a first vertical sidewall of said gate dielectric is located between a first parallel pair of vertical planes including sidewalls of said first dielectric spacer, and a second vertical sidewall of said gate dielectric is located between a second parallel pair of vertical planes including sidewalls of said second dielectric spacer.
8 . The semiconductor structure of claim 1 , further comprising another dielectric spacer laterally surrounding said gate stack, overlying said first dielectric spacer and said second dielectric spacer, and topologically homeomorphic to a torus.
9 . The semiconductor structure of claim 8 , further comprising:
a planarization dielectric layer laterally surrounding said another dielectric spacer; and
a semiconductor-element-including dielectric material layer comprising a dielectric material including at least one semiconductor atom and overlying said planarization dielectric layer and said another dielectric spacer.
10 . The semiconductor structure of claim 9 , wherein sidewall of said gate dielectric vertically extend from said body region to a horizontal plane including a top surface of said semiconductor-element-including dielectric material layer.
11 . A semiconductor structure comprising:
a semiconductor material portion including a body region, a source region, and a drain region;
a gate stack including a gate dielectric and a gate electrode, wherein said gate stack straddles said body region; and
a dielectric spacer laterally surrounding said gate stack, wherein all sidewalls of said dielectric spacer are within vertical planes.
12 . The semiconductor structure of claim 11 , further comprising a dielectric material layer overlying said dielectric spacer and including an opening therein, wherein a periphery of said opening is vertically coincident with vertical interfaces between said gate stack and said dielectric spacer.
13 . The semiconductor structure of claim 12 , wherein a concave surface of said dielectric spacer contacts a convex surface of said dielectric material layer.
14 . The semiconductor structure of claim 12 , further comprising a planarization dielectric layer laterally surrounding said dielectric spacer and underlying said dielectric material layer, wherein a contiguous outer periphery of vertically downward-protruding portions of said dielectric material layer contacts sidewalls of said planarization dielectric layer.
15 . The semiconductor structure of claim 14 , wherein said contiguous outer periphery is vertically coincident with outer sidewalls of said dielectric spacer.
16 . A method of forming a semiconductor structure comprising:
forming a disposable dielectric gate structure over a semiconductor material portion;
forming a source region, a drain region, and a body region in said semiconductor material portion;
forming a raised source region and a raised drain region on said source region and said drain region, respectively, wherein said raised source region and said raised drain region contact sidewalls of said disposable dielectric gate structure;
forming a planarization dielectric layer over said raised source region and said raised drain region and around said disposable dielectric gate structure;
removing said disposable dielectric gate structure selective to said planarization dielectric layer to form a gate cavity; and
converting surface portions of said raised source region and said raised drain region into a first dielectric spacer and a second dielectric spacer.
17 . The method of claim 16 , wherein said converting of said surface portions of said raised source region and said raised drain region is performed employing a thermal oxidation process, a thermal nitridation process, a thermal oxynitridation process, a plasma oxidation process, a plasma nitridation process, a plasma oxynitridation process, or a combination thereof.
18 . The method of claim 16 , further comprising:
forming a diffusion-resistant dielectric material liner on said semiconductor material portion, wherein said disposable dielectric gate structure is formed over said diffusion-resistant dielectric material liner;
patterning said diffusion-resistant dielectric material liner into a dielectric material portion, wherein said dielectric material portion protects a portion of said body region from conversion into a dielectric material during said converting of said surface portions of said raised source region and said raised drain region.
19 . The method of claim 16 , further comprising forming a replacement gate structure including a gate dielectric and a gate electrode within said gate cavity.
20 . The method of claim 16 , further comprising:
recessing a top surface of said planarization dielectric layer relative to a top surface of said disposable dielectric gate structure;
forming a semiconductor material layer over said planarization dielectric layer; and
converting said semiconductor material layer into a semiconductor-element-including dielectric material layer simultaneously with said converting of said surface portions of said raised source region and said raised drain region.
21 . The method of claim 20 , further comprising:
depositing a conformal dielectric material layer in said gate cavity after said converting of said surface portions of said raised source region and said raised drain region; and
forming an additional dielectric spacer by anisotropically etching said conformal dielectric material layer employing said semiconductor-element-including dielectric material layer as an etch mask.
22 . A method of forming a semiconductor structure comprising:
forming a dielectric gate structure over a semiconductor material portion;
forming a source region, a drain region, and a body region in said semiconductor material portion;
forming a raised source region and a raised drain region on said source region and said drain region, respectively, wherein said raised source region and said raised drain region contact sidewalls of said dielectric gate structure;
forming a planarization dielectric layer over said raised source region and said raised drain region and around said dielectric gate structure;
forming a dielectric material layer having an opening therein over said planarization dielectric layer, wherein a periphery of said opening is within an area defined by sidewalls of said dielectric gate structures; and
forming a dielectric spacer and a gate cavity by anisotropically etching said dielectric gate structure employing said dielectric material layer as an etch mask, wherein a remaining contiguous portion of said dielectric gate structure constitutes said dielectric spacer.
23 . The method of claim 22 , further comprising forming a replacement gate structure including a gate dielectric and a gate electrode within said gate cavity.
24 . The method of claim 22 , further comprising:
recessing said planarization dielectric layer below a top surface of said dielectric gate structure; and
etching said dielectric gate structure isotropically, wherein a top surface of said dielectric gate structure protrudes above a recessed surface of said planarization dielectric layer and peripheral surfaces of said dielectric gate structure adjoin sidewalls of said planarization dielectric layer below said recessed surface of said planarization dielectric layer after said etching of said dielectric gate structure.
25 . The method of claim 24 , wherein said dielectric material layer having said opening therein is formed directly on a recessed surface of said planarization dielectric layer and directly on portions of said sidewalls of said planarization dielectric layer.