Three dimensional resistive memory
View Patent ↗A memory device includes a stack of layers comprising a plurality of alternating layers of continuous electrically conductive material word line layers with layers of continuous electrically insulating material. A plurality of vias vertically extend through the stack of layers and a vertical bit line is disposed within each via. A layer of switching material separates the vertical bit line from the stack of layers, thereby forming an array of RRAM cells.
1. A memory device comprising:
a stack of layers comprising a plurality of alternating layers of continuous electrically conductive material with layers of continuous electrically insulating material, each layer of continuous electrically conductive material forming a word line plane;
a plurality of vias vertically extending through the stack of layers, wherein the plurality of vias comprise longitudinally extending rectangular trench vias;
a vertical bit line disposed within each via, wherein each bit line is electrically isolated from adjacent via bit lines; and
a layer of switching material separating each longitudinally extending rectangular trench via from the stack of layers, thereby forming an array of RRAM cells, wherein the layer of switching material comprises chalcogenide glass.
2. The memory device according to claim 1 , wherein the layer of switching material forms parallel layers that separate the vertical bit line from the stack of layers.
3. The memory device according to claim 2 , further comprising a plurality of vertically extending layers of electrically insulating material separating the parallel layers of switching material and separating the vertical bit line into a plurality of vertical bit lines longitudinally extending along the rectangular trench via.
4. The memory device according to claim 3 , wherein the vertical bit lines longitudinally extending along the rectangular trench via are electrically isolated from each other.