Display system with display panel and display controller and driver having moving picture interface
No flicker is displayed on the display screen during display of moving pictures and power consumption can be reduced by adding a high quality moving picture display function. Moreover, the number of times of transfer of moving pictures by comprising a still-picture • text • system • I/O bus • interface and a moving picture interface (external display interface), providing a display operation change register (DM) and a RAM access change register (RM) which are changed selectively depending on display content (display mode) displayed on a display device and displaying the display data on the display device via a picture memory even in the moving picture display mode.
1. A display system comprising:
a display panel; and
a display controller and driver coupled to the display panel and on a semiconductor chip,
wherein the display controller and driver comprises
data terminals to which data is supplied external to the display system;
a first terminal to which a vertical synchronization signal is supplied external to the display system;
a second terminal to which a horizontal synchronization signal is supplied external to the display system;
a third terminal to which a dotclock is supplied external to the display system;
a clock generation circuit for generating an internal operation clock signal;
an external display interface which is coupled to the data terminals and the first to third terminals;
a system interface which is coupled to the data terminals;
a memory which stores picture data to be displayed to the display panel;
a display drive circuit which is coupled to the memory and which provides display data to the display panel in accordance with the picture data read from the memory;
a first register comprising
a first state in which the memory is enabled to be read in synchronization with the internal clock signal; and
a second state in which the memory is enabled to be read in synchronization with the vertical synchronization signal, the horizontal synchronization signal, and the dotclock; and
a second register comprising
a first state in which the memory is enabled to write the data provided to the system interface via the data terminals; and
a second state in which the memory is enabled to write the data provided to the external display interface via the data terminals.
2. The display system according to claim 1 ,
wherein the display controller and driver further comprises:
a fourth terminal coupled to the external display interface and to which an enable signal is supplied, wherein the enable signal has an active state and an non-active state, and
wherein the data supplied to the external display interface via the data terminals is written into the memory in accordance with an active state of the enable signal.
3. The display system according to claim 1 ,
wherein the display controller and driver further comprises:
a third register for storing a start address and an end address of an area in the memory where the data supplied via the external display interface is to be written.
4. The display system according to claim 1 ,
wherein the first and the second registers are set by an instruction supplied to the system interface via the data terminals.
5. The display system according to claim 1 ,
wherein the display controller and driver further comprises:
fifth, sixth, and seventh terminals each coupled to the system interface and to which a chip select signal, a register select signal, and a write signal are supplied, respectively.
6. The display system according to claim 1 ,
wherein the data includes still picture data when the first register is in its first state and the second register is in its first state,
wherein the data includes moving picture data when the first register is in its second state and the second register is in its second state, and
wherein the data includes still picture data when the first register is in its second state and the second register is in its first state.
7. The display system according to claim 6 ,
wherein the first register has two bits,
wherein the second register has one bit,
wherein the two bits of the first register are 00 in the first state of the first register,
wherein the two bits of the first register are 01 in the second state of the first register,
wherein the one bit of the second register is 0 in the first state of the second register, and
wherein the one bit of the second register is 1 in the second state of the second register.
8. The display system according to claim 7 ,
wherein the first register has a third state in which the memory is enabled to be read in synchronization with the internal clock signal and the vertical synchronization signal, and
wherein the data includes moving picture data when the first register is in its third state and the second register is in its first state.
9. The display system according to claim 8 ,
wherein the two bits of the first register are 10 in the third state of the first register.
10. The display system according to claim 1 ,
wherein the first register has two bits,
wherein the second register has one bit,
wherein the two bits of the first register are 00 in the first state of the first register,
wherein the two bits of the first register are 01 in the second state of the first register,
wherein the one bit of the second register is 0 in the first state of the second register, and
wherein the one bit of the second register is 1 in the second state of the second register.
11. The display system according to claim 10 ,
wherein the first register has a third state in which the memory is enabled to be read in synchronization with the internal clock signal and the vertical synchronization signal, and
wherein the data includes moving picture data when the first register is in its third state and the second register is in its first state.
12. The display system according to claim 11 ,
wherein the two bits of the first register are 10 in the third state of the first register.