IP Library Granted Patent US 8,865,588
Granted Patent B2
US 8,865,588 · App. 14/140,126 · Granted Oct 21, 2014

Method of manufacturing semiconductor device

Inventor: Takeshi Kagawa (Kuwana, JP)
Assignee: Fujitsu Semiconductor Limited
H01L21/76895H01L27/0207H01L21/76897
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Quick Facts
Patent No.
US 8,865,588
App. No.
14/140,126
Granted
Oct 21, 2014
Kind
B2
Abstract

A method of manufacturing a semiconductor device includes forming a first interconnection and a second interconnection above a semiconductor substrate, forming a first sidewall insulating film on a side wall of the first interconnection, and a second sidewall insulating film on a side wall of the second interconnection, forming a conductive film above the semiconductor substrate with the first interconnection, the first sidewall insulating film, the second interconnection and the second sidewall insulating film formed on, and selectively removing the conductive film above the first interconnection and the second interconnection to form in a region between the first interconnection and the second interconnection a third interconnection formed of the conductive film and spaced from the first interconnection and the second interconnection by the first sidewall insulating film and the second sidewall insulating film.

Claims (25)

1. A method of manufacturing a semiconductor device comprising:

forming a first interconnection and a second interconnection above a semiconductor substrate;

forming a first sidewall insulating film on a side wall of the first interconnection, and a second side wall insulating film on a side wall of the second interconnection;

forming a sacrificial film above the semiconductor substrate with the first interconnection, the first sidewall insulating film, the second interconnection and the second sidewall insulating film formed on;

forming an opening in the sacrificial film in a region between the first interconnection and the second interconnection for a third interconnection to be formed in;

forming a conductive film above the semiconductor substrate with the sacrificial film formed on; and

selectively removing the conductive film above the sacrificial film to form the third interconnection of the conductive film in the opening, spaced from the first interconnection and the second interconnection by the first sidewall insulating film and the second sidewall insulating film.

2. The method of manufacturing a semiconductor device according to claim 1 , wherein

selectively removing the conductive film above the sacrificial film includes planarizing the conductive film and etching back the conductive film.

3. The method of manufacturing a semiconductor device according to claim 2 , wherein

in etching back the conductive film, the conductive film is etched back to a film thickness of the third interconnection to be formed.

4. The method of manufacturing a semiconductor device according to claim 1 , wherein

forming the sacrificial film includes depositing the sacrifice film and planarizing the sacrificial film.

5. The method of manufacturing a semiconductor device according to claim 1 , wherein

the sacrificial film is an amorphous carbon film.

6. The method of manufacturing a semiconductor device according to claim 1 , wherein

the first sidewall insulating film includes a first insulating portion formed on the side wall of the first interconnection, and a second insulating portion formed on the first insulating portion, and

the second sidewall insulating film includes a third insulating portion formed on the side wall of the second interconnection, and a fourth insulating portion formed on the third insulating portion.

7. The method of manufacturing a semiconductor device according to claim 6 , further comprising, after forming a third interconnection:

removing the second insulating portion of the first sidewall insulating film, and the fourth insulating portion of the second sidewall insulating film.

8. The method of manufacturing a semiconductor device according to claim 1 , wherein

the first interconnection and the second interconnection are arranged in parallel with each other.

9. The method of manufacturing a semiconductor device according to claim 1 , wherein

the first interconnection and the second interconnection are a gate electrode, and

the third interconnection is an interconnection interconnecting active regions formed on the semiconductor substrate or a lead-out line from an active region of the semiconductor substrate.

Assignments (2)
CHANGE OF ADDRESS Recorded Dec 23, 2016
From: FUJITSU SEMICONDUCTOR LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 041188/0401 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 16, 2014
From: KAGAWA, TAKESHI
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 033748/0394 →
Priority Claims (1)
JP 2011-198023 · Sep 12, 2011 · national
Continuity (2)
Division 13562818 · Jul 31, 2012
Related Publication 20140113441A1 · Apr 24, 2014