Semiconductor device
A method for sensing data in a resistive memory device including a sense amplifier with an input coupled to a bitline through a capacitor includes activating a word line to form a current path through a resistive memory cell to the bitline, precharging the bitline to a first precharge voltage and precharging the input of the sense amplifier to a second precharge voltage between the first precharge voltage and the decision threshold of the sense amplifier, disabling, after a first predetermined period of time, precharge of the bit line and precharge of the input of the sense amplifier, and latching data at an output of the sense amplifier after a second predetermined period of time.
1. A method for sensing data in a resistive memory device comprising a sense amplifier with an input coupled to a bitline through a capacitor, the method comprising:
activating a word line to form a current path through a resistive memory cell to the bitline;
precharging the bitline to a first precharge voltage and precharging the input of the sense amplifier to a second precharge voltage between the first precharge voltage and the decision threshold of the sense amplifier;
disabling, after a first predetermined period of time, precharge of the bit line and precharge of the input of the sense amplifier; and
latching data at an output of the sense amplifier after a second predetermined period of time.
2. The method as claimed in claim 1 , wherein the first precharge voltage comprises a supply voltage.
3. The method as claimed in claim 2 , wherein the supply voltage includes Vcc.
4. The method as claimed in claim 1 , further comprising maintaining the bitline at the first precharge level with a current higher than that which the resistive memory cell provides in a high resistance state and lower than that which the resistive memory cell provides in a low resistance state.
5. The method as claimed in claim 1 , wherein the second precharge voltage is generated with a first inverter including an inverter input connected to an inverter output.
6. The method as claimed in claim 5 , wherein the sense amplifier comprises a second inverter.
7. The method as claimed in claim 6 , wherein a P:N ratio of the first inverter is higher than a P:N ratio of the second inverter.
8. The method as claimed in claim 1 , wherein the sense amplifier comprises a variable threshold inverter in which an inverter input is coupled to an inverter output during precharge.
9. The method as claimed in claim 8 , wherein the variable threshold inverter comprises an MOS transistor including a source coupled to a power supply voltage, a drain coupled to the inverter output, and a gate connected to a precharge control signal.
10. The method as claimed in claim 9 , wherein the MOS transistor comprises an NMOS transistor including a source coupled to Vss.
11. The method as claimed in claim 10 , wherein the precharge control signal is low during precharge.
12. The method as claimed in claim 1 , wherein the resistive memory cell comprises a phase change memory cell.
13. The method as claimed in claim 12 , wherein the phase change memory cell comprises a chalcogenide material.
14. The method as claimed in claim 12 , wherein the phase change memory cell has a low resistance crystalline state and a high resistance amorphous state.
15. The method as claimed in claim 1 , wherein the resistive memory cell includes a terminal coupled to a supply voltage.
16. The method as claimed in claim 15 , wherein the supply voltage includes Vss.