Method for Flip-Chip Bonding Using Copper Pillars
A bonding pad arrangement and method of bonding a flip-chip semiconductor device to a substrate using copper pillars and solder to join die pads on the flip-chip to substrate pads on the substrate. Each substrate pad has an offset from a respective die pad at specific temperature, the offset for each of the substrate pads is substantially the same, and the offset is determined as a function of the size of the flip-chip device, a difference between a solidification temperature of the solder and the specific temperature, and a difference between a coefficient of thermal expansion of the flip-chip device and a coefficient of thermal expansion of the substrate. Alternatively, the offset for each of the substrate pads is the above-determined offset scaled as a function of a distance the respective die pad is from the centroid of the device.
1 . A package comprising:
a flip-chip device having a centroid and a plurality of die pads thereon;
a plurality of copper pillars, each copper pillar disposed on a respective die pad of the plurality of die pads;
a substrate having a plurality of substrate pads thereon; and
a solder layer disposed between each one of the plurality of copper pillars and its respective substrate pad;
wherein each substrate pad has an offset from a respective die pad at specific temperature, the offset for each of the substrate pads of the is substantially the same, and the offset is determined as a function of the size of the flip-chip device, a difference between a solidification temperature of the solder and the specific temperature, and a difference between a coefficient of thermal expansion of the flip-chip device and a coefficient of thermal expansion of the substrate.
2 . The package of claim 1 wherein the offset is determined in accordance with the following relationship;
offset=DNP max ×(CTE substrate −CTE device )×( T solidification −T );
where: offset is the amount of offset between a substrate pad and its respective die pad;
DNP max is a farthest distance on the device from the device centroid;
CTE substrate and CTE device are the coefficients of expansion of the substrate and flip-chip device, respectively; and
T solidification and T are the solder solidification and the specific temperatures, respectively.
3 . The package of claim 1 wherein the specific temperature is one of a room temperature an expected operating temperature.
4 . The package of claim 1 wherein the flip-chip device comprises a material selected from the group consisting of silicon, gallium arsenide, indium phosphide, and a combination thereof, and the substrate is selected from the group consisting of glass-epoxy, polytetrafluoroethylene, ceramic, silicon, glass, and a combination thereof.
5 . The package of claim 1 further comprising an overmold over the flip-chip device and the substrate.
6 . The package of claim 1 wherein the substrate has a centroid aligned with the centroid of the device.
7 . A package comprising:
a flip-chip device having a centroid and a plurality of die pads thereon;
a plurality of copper pillars, each copper pillar disposed on a respective die pad of the plurality of die pads;
a substrate having a plurality of substrate pads thereon; and
a solder layer disposed between each one of the plurality of copper pillars and its respective substrate pad;
wherein each substrate pad has an offset from a respective die pad at specific temperature, the offset for each of the substrate pads of the is determined as a function of the size of the flip-chip device, a difference between a solidification temperature of the solder and the specific temperature, a difference between a coefficient of thermal expansion of the flip-chip device and a coefficient of thermal expansion of the substrate, and a distance the respective die pad is with respect to the centroid.
8 . The package of claim 1 wherein the offset of each one of the plurality of substrate pads is determined in accordance with the following relationship:
offset=DNP max ×(CTE substrate −CTE device )×( T solidification −T )×(1−DNP pad /DNP max )
where: offset is the amount of offset between a substrate pad and its a respective die pad;
DNP max is a farthest distance on the device from the device centroid;
DNP pad is a distance the die pad on the device is from the device centroid;
CTE substrate and CTE device are the coefficients of expansion of the substrate and flip-chip device, respectively; and
T solidification and T are the solder solidification and the specific temperatures, respectively.
9 . The package of claim 7 wherein the specific temperature is one of a room temperature or an expected operating temperature.
10 . The package of claim 7 wherein the flip-chip device comprises a material selected from the group consisting of silicon, gallium arsenide, and indium phosphide, and the substrate is selected from the group consisting of glass-epoxy, polytetrafluoroethylene ceramic, silicon, glass, and a combination thereof.
11 . The package of claim 7 further comprising an overmold over the flip-chip device and the substrate.
12 . The package of claim 7 wherein the substrate has a centroid aligned with the centroid of the device.
13 . A method comprising the steps of:
A) providing a flip-chip device having a centroid and a plurality of die pads thereon;
B) providing a plurality of copper pillars on respective die pads of the plurality of die pads;
C) forming a layer of solder on each of the copper pillars;
D) providing a substrate having a plurality of substrate pads, each of the plurality of substrate pads positioned on the substrate to align with a respective one of the copper pillars;
E) bringing the flip-chip device in proximity to the substrate until all the solder layers are in contact with respective substrate pads to form a device-substrate combination;
F) applying heat to the device-substrate combination to raise the temperature thereof until all of the solder melts; and
G) cooling the device-substrate combination to a temperature at which all of the solder solidifies;
wherein each substrate pad has an offset from a respective die pad at specific temperature, the offset for each of the substrate pads is substantially the same, and the offset is determined as a function of the size of the flip-chip device, a difference between a solidification temperature of the solder and the specific temperature, and a difference between a coefficient of thermal expansion of the flip-chip device and a coefficient of thermal expansion of the substrate.
14 . The method of claim 13 wherein the offset is determined in accordance with the following relationship:
offset=DNP max ×(CTE substrate −CTE device )×( T solidification −T );
where: offset is the amount of offset between a substrate pad and its respective die pad;
DNP max is a farthest distance on the device from the device centroid;
CTE substrate and CTE device are the coefficients of expansion of the substrate and flip-chip device, respectively; and
T solidification and T are the solder solidification and the specific temperatures, respectively.
15 . The method of claim 13 wherein each copper pillar has a height above a die pad and each of the solder layers has a height above a copper pillar, and a sum of the height of each copper pillar and its respective solder layer prior to step F) is between 5 microns and 130 microns.
16 . The method of claim 15 wherein each copper pillar has a diameter of 80 microns or less and a sum of the height of each copper pillar and its respective solder layer prior to step is 80 microns or less.
17 . The method of claim 13 wherein the flip-chip device comprises a material selected from the group consisting of silicon, gallium arsenide, indium phosphide, and a combination thereof, and the substrate is selected from the group consisting of glass-epoxy, polytetrafluoroethylene, ceramic, silicon, glass, a combination thereof, and a combination thereof.
18 . The method of claim 13 further comprising the steps of:
H) forming, after step G), an underfill layer between the flip-chip device and the substrate.
19 . The method of claim 18 further comprising the step of:
forming, after step H), an overmold on the flip-chip device and the substrate.
20 . The method of claim 13 wherein the copper pillar is formed by the steps of:
depositing, a photoresist onto the flip-chip device;
patterning the photoresist to expose the plurality of die pads;
plating copper onto the exposed die pads; and
removing the photoresist.
21 . A method comprising the steps of
A) providing a flip-chip device having a centroid and a plurality of die pads thereon;
B) providing a plurality of copper pillars on respective die pads of the plurality of die pads;
C) forming a layer of solder on each of the copper pillars;
D) providing a substrate having a plurality of substrate pads, each of the plurality of substrate pads positioned on the substrate to align with a respective one of the copper pillars;
E) bringing the flip-chip device in proximity to the substrate until all the solder layers are in contact with respective substrate pads to form a device-substrate combination;
F) applying heat to the device-substrate combination to raise the temperature thereof until all of the solder melts; and
G) cooling the device-substrate combination to a temperature at which all of the solder solidifies;
wherein each substrate pad has an offset from a respective die pad at specific temperature, the offset for each of the substrate pads of the is determined as a function of the size of the flip-chip device, a difference between a solidification temperature of the solder and the specific temperature, a difference between a coefficient of thermal expansion of the flip-chip device and a coefficient of thermal expansion of the substrate, and a distance the respective die pad is with respect to the centroid.
22 . The method of claim 21 wherein the offset of each one of the plurality of substrate pads is determined in accordance with the following relationship:
offset=DNP max ×(CTE substrate −CTE device )×( T solidification −T )×(1−DNP pad /DNP max )
where: offset is the amount of offset between a substrate pad and its respective die pad;
DNP max is a farthest distance on the device from the device centroid;
DNP pad is a distance the die pad on the device is from the device centroid;
CTE substrate and CTE device are the coefficients of expansion of the substrate and flip-chip device, respectively; and
T solidification and T are the solder solidification and the specific temperatures, respectively.
23 . The method of claim 21 wherein each copper pillar has a height above a die pad and each of the solder layers has a height above a copper pillar, and a sum of the height of each copper pillar and its respective solder layer prior to step F) is between 5 microns and 130 microns.
24 . The method of claim 21 wherein each copper pillar has a diameter of 80 microns or less and a sum of the height of each copper pillar and its respective solder layer prior to step F) is 80 microns or less.
25 . The method of claim 21 wherein the flip-chip device comprises a material selected from the group consisting of silicon, gallium arsenide, indium phosphide, and a combination thereof, and the substrate is selected from the group consisting of glass-epoxy, polytetrafluoroethylene, ceramic, silicon, glass, a combination thereof, and a combination thereof.
26 . The method of claim 21 further comprising the steps of:
H) forming, after step G), an underfill layer between the flip-chip device and the substrate.
27 . The method of claim 26 further comprising the step of:
forming, after step H), an overmold on the flip-chip device and the substrate.
28 . The method of claim 21 wherein the copper pillar is formed by the steps of:
depositing a photoresist onto the flip-chip device;
patterning, the photoresist to expose the plurality of die pads;
plating copper onto the exposed die pads; and
removing the photoresist.