IP Library Granted Patent US 8,954,830
Granted Patent B2
US 8,954,830 · App. 14/231,087 · Granted Feb 10, 2015

Decoder, reception apparatus, decoding method, and reception method

Inventors: Yutaka Murakami (Osaka, JP); Shutai Okamura (Osaka, JP)
Assignee: Panasonic Intellectual Property Corporation of America
H03M13/1125H03M13/116H03M13/6362H03M13/6527H03M13/15H03M13/005
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,954,830
App. No.
14/231,087
Granted
Feb 10, 2015
Kind
B2
Abstract

Disclosed are an encoder, a transmitting device, a coding method and a transmission method with which the transmission amount is reduced and a deterioration in transmission efficiency is suppressed while improving reception quality when QC-LDPC or a like block coding is used. A puncture pattern setting unit searches for a puncture pattern for each integral multiple of the number of columns or for each divisor of the number of columns of a sub block matrix that forms a check matrix (H) of a QC-LDPC code, and a puncture unit (data reduction unit) switches the puncture pattern for each integral multiple of the number of columns or for each divisor of the number of columns of the sub block matrix that forms the check matrix of the QC-LDPC code.

Claims (330)

1. A decoder comprising:

a log likelihood ratio calculator configured to calculate a first log likelihood ratio sequence using a second coded sequence obtained by removing bits from a first coded sequence s, wherein:

the first coded sequence s is made up of z×n b bits and satisfies equation 1-1, equation 1-2 and equation 1-3, where:

GH T =0  (Equation 1-1)

S T =Gu T   (Equation 1-2)

Hs= 0  (Equation 1-3)

where H is a parity check matrix of a low density parity check (LDPC) code of z×m b rows and z×n b columns configured by arranging submatrixes of z rows and z columns in m b rows and n b columns, G is a generator matrix holding a relationship of equation 1-1 with the parity check matrix H of the LDPC code, and the coded sequence s is a coded sequence made up of z×n b bits;

the equation 1-1, the equation 1-2 and the equation 1-3 are generated for information bit sequence u;

the second coded sequence is obtained by removing bits based on a puncturing pattern in a cycle of y bits starting from a first bit of the first coded sequence s;

the puncturing pattern includes a determined number of bits to be punctured for each cycle, and is used for (i) one column group from a plurality of column groups having column weight of 3 in a matrix H′b1 that corresponds to the information bit sequence u and includes a plurality of column groups having column weight of equal to or greater than 3, of a parity check matrix H of a low density parity check (LDPC) code, and (ii) two column groups in a matrix H′b2 that corresponds to a parity bit sequence, of the parity check matrix H of the LDPC code;

one of the two column groups in the matrix H′b2 becomes a zero matrix in rows of the parity check matrix H that corresponds to a zero matrix included in the column group in the matrix H′b1; and

the y is any divisor of a number of columns z of the parity check matrix H of the LDPC code;

a generator configured to generate a second log likelihood ratio sequence having a predetermined log likelihood ratio inserted in the first log likelihood ratio sequence based on the puncturing pattern; and

a BP decoder configured to decode the second log likelihood ratio sequence based on the parity check matrix H to output the information bit sequence u.

2. The decoder according to claim 1 , wherein the parity check matrix H of the LDPC code is defined by an equation:

H

=

[

P

0

,

0

P

0

,

1

P

0

,

2

P

0

,

n

b

-

2

P

0

,

n

b

-

1

P

1

,

0

P

1

,

1

P

1

,

2

P

1

,

n

b

-

2

P

1

,

n

b

-

1

P

2

,

0

P

2

,

1

P

2

,

2

P

2

,

n

b

-

2

P

2

,

n

b

-

1

P

m

b

-

1

,

0

P

m

b

-

1

,

1

P

m

b

-

1

,

2

P

m

b

-

1

,

n

b

-

2

P

m

b

-

1

,

n

b

-

1

]

where P i,j is a cyclic permutation matrix of a unit matrix of z rows and z columns or zero matrix of z rows and z columns.

3. The decoder according to claim 2 , wherein the LDPC code is a quasi-cyclic low density parity check (QC-LDPC) code.

4. A reception apparatus comprising:

a receiver configured to receive a signal including a second coded sequence obtained by removing bits from a first coded sequence s, wherein:

the first coded sequence s is made up of z×n b bits and satisfies equation 1-1, equation 1-2 and equation 1-3, where:

GH T =0  (Equation 1-1)

s T =Gu T   (Equation 1-2)

Hs= 0  (Equation 1-3)

where H is a parity check matrix of a low density parity check (LDPC) code of z×m b rows and z×n b columns configured by arranging submatrixes of z rows and z columns in m b rows and n b columns, G is a generator matrix holding a relationship of equation 1-1 with the parity check matrix H of the LDPC code, and the coded sequence s is a coded sequence made up of z×n b bits;

the equation 1-1, the equation 1-2 and the equation 1-3 are generated for information bit sequence u;

the second coded sequence is obtained by removing bits based on a puncturing pattern in a cycle of y bits starting from a first bit of the first coded sequence s;

the puncturing pattern includes a determined number of bits to be punctured for each cycle, and is used for (i) one column group from a plurality of column groups having column weight of 3 in a matrix H′b1 that corresponds to the information bit sequence u and includes a plurality of column groups having column weight of equal to or greater than 3, of a parity check matrix H of a low density parity check (LDPC) code, and (ii) two column groups in a matrix H′b2 that corresponds to a parity bit sequence, of the parity check matrix H of the LDPC code;

one of the two column groups in the matrix H′b2 becomes a zero matrix in rows of the parity check matrix H that corresponds to a zero matrix included in the column group in the matrix H′b1; and

the y is any divisor of a number of columns z of the parity check matrix H of the LDPC code;

a log likelihood ratio calculator configured to calculate a first log likelihood ratio sequence using the second coded sequence;

a generator configured to generate a second log likelihood ratio sequence having a predetermined log likelihood ratio inserted in the first log likelihood ratio sequence based on the puncturing pattern; and

a BP decoder configured to decode the second log likelihood ratio sequence based on the parity check matrix H to output the information bit sequence u.

5. The decoding method according to claim 4 , wherein the parity check matrix H of the LDPC code is defined by an equation:

H

=

[

P

0

,

0

P

0

,

1

P

0

,

2

P

0

,

n

b

-

2

P

0

,

n

b

-

1

P

1

,

0

P

1

,

1

P

1

,

2

P

1

,

n

b

-

2

P

1

,

n

b

-

1

P

2

,

0

P

2

,

1

P

2

,

2

P

2

,

n

b

-

2

P

2

,

n

b

-

1

P

m

b

-

1

,

0

P

m

b

-

1

,

1

P

m

b

-

1

,

2

P

m

b

-

1

,

n

b

-

2

P

m

b

-

1

,

n

b

-

1

]

where P i,j is a cyclic permutation matrix of a unit matrix of z rows and z columns or zero matrix of z rows and z columns.

6. A decoding method comprising:

calculating, by a processor, a first log likelihood ratio sequence using a second coded sequence obtained by removing bits from a first coded sequence s, wherein:

the first coded sequence s is made up of z×n b bits and satisfies equation 1-1, equation 1-2 and equation 1-3, where:

GH T =0  (Equation 1-1)

s T =GU T   (Equation 1-2)

Hs= 0  (Equation 1-3)

where H is a parity check matrix of an low density parity check (LDPC) code of z×m b rows and z×n b columns configured by arranging submatrixes of z rows and z columns in m b rows and n b columns, G is a generator matrix holding a relationship of equation 1-1 with the parity check matrix H of the LDPC code, and the coded sequence s is a coded sequence made up of z×n b bits;

the equation 1-1, the equation 1-2 and the equation 1-3 are generated for information bit sequence u;

the second coded sequence is obtained by removing bits based on a puncturing pattern in a cycle of y bits starting from a first bit of the first coded sequence s;

the puncturing pattern includes a determined number of bits to be punctured for each cycle, and is used for (i) one column group from a plurality of column groups having column weight of 3 in a matrix H′b1 that corresponds to the information bit sequence u and includes a plurality of column groups having column weight of equal to or greater than 3, of a parity check matrix H of a low density parity check (LDPC) code, and (ii) two column groups in a matrix H′b2 that corresponds to a parity bit sequence, of the parity check matrix H of the LDPC code;

one of the two column groups in the matrix H′b2 becomes a zero matrix in rows of the parity check matrix H that corresponds to a zero matrix included in the column group in the matrix H′b1; and

the y is any divisor of a number of columns z of the parity check matrix H of the LDPC code;

generating a second log likelihood ratio sequence having a predetermined log likelihood ratio inserted in the first log likelihood ratio sequence based on the puncturing pattern; and

decoding the second log likelihood ratio sequence based on the parity check matrix H to output the information bit sequence u.

7. The decoding method according to claim 6 , wherein the LDPC code is a quasi-cyclic low density parity check (QC-LDPC) code.

8. A reception method comprising:

receiving a signal including a second coded sequence obtained by removing bits from a first coded sequence s, wherein:

the first coded sequence s is made up of z×n b bits and satisfies equation 1-1, equation 1-2 and equation 1-3, where:

GH T =0  (Equation 1-1)

s T =GU T   (Equation 1-2)

Hs= 0  (Equation 1-3)

where H is a parity check matrix of an low density parity check (LDPC) code of z×m b rows and z×n b columns configured by arranging submatrixes of z rows and z columns in m b rows and n b columns, G is a generator matrix holding a relationship of equation 1-1 with the parity check matrix H of the LDPC code, and the coded sequence s is a coded sequence made up of z×n b bits;

the equation 1-1, the equation 1-2 and the equation 1-3 are generated for information bit sequence u;

the second coded sequence is obtained by removing bits based on a puncturing pattern in a cycle of y bits starting from a first bit of the first coded sequence s;

the puncturing pattern includes a determined number of bits to be punctured for each cycle, and is used for (i) one column group from a plurality of column groups having column weight of 3 in a matrix H′b1 that corresponds to the information bit sequence u and includes a plurality of column groups having column weight of equal to or greater than 3, of a parity check matrix H of a low density parity check (LDPC) code, and (ii) two column groups in a matrix H′b2 that corresponds to a parity bit sequence, of the parity check matrix H of the LDPC code;

one of the two column groups in the matrix H′b2 becomes a zero matrix in rows of the parity check matrix H that corresponds to a zero matrix included in the column group in the matrix H′b1; and

the y is any divisor of a number of columns z of the parity check matrix H of the LDPC code;

calculating, by a processor, a first log likelihood ratio sequence using the second coded sequence;

generating a second log likelihood ratio sequence having a predetermined log likelihood ratio inserted in the first log likelihood ratio sequence based on the puncturing pattern; and

decoding the second log likelihood ratio sequence based on the parity check matrix H to output the information bit sequence u.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 27, 2014
From: PANASONIC CORPORATION
To: PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA
Reel/Frame 033033/0163 →
Priority Claims (2)
JP 2008-264382 · Oct 10, 2008 · national
JP 2008-290022 · Nov 12, 2008 · national
Continuity (4)
Continuation 14065020 · Oct 28, 2013
Continuation 13900264 · May 22, 2013
Continuation 13122942
Related Publication 20140215287A1 · Jul 31, 2014