IP Library Granted Patent US 9,813,224
Granted Patent B2
US 9,813,224 · App. 14/255,491 · Granted Nov 7, 2017

Digital processor having instruction set with complex angle function

Inventor: Kameran Azadet (San Ramon, CA)
Assignee: Intel Corporation
H04L5/1461G06F9/30036G06F17/15G06F17/50G06F17/5009H04B1/0475H04B1/525H04B1/62H04J11/004H04L1/0043H04L25/03012H04L25/03343H04L25/08H04L27/367H04L27/368H04B2001/0425
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Quick Facts
Patent No.
US 9,813,224
App. No.
14/255,491
Granted
Nov 7, 2017
Kind
B2
Abstract

A digital processor, such as a vector processor or a scalar processor, is provided having an instruction set with a complex angle function. A complex angle is evaluated for an input value, x, by obtaining one or more complex angle software instructions having the input value, x, as an input; in response to at least one of the complex angle software instructions, performing the following steps: invoking at least one complex angle functional unit that implements the one or more complex angle software instructions to apply the complex angle function to the input value, x; and generating an output corresponding to the complex angle of the input value, x, using one or more multipliers of a Multiply Accumulate (MAC) unit of the digital processor, wherein the complex angle software instruction is part of an instruction set of the digital signal processor. Multiplication operations optionally employ one or more multipliers of the MAC unit of the digital processor.

Claims (27)

1. A method performed by a digital processor for evaluating a complex angle for an input value, x, comprising:

obtaining one or more complex angle software instructions having said input value, x, as an input;

in response to at least one of said complex angle software instructions, performing the following steps:

invoking at least one complex angle functional unit that implements said one or more complex angle software instructions to apply said complex angle function to said input value, x; and

generating an output corresponding to said complex angle of said input value, x, using one or more multipliers of a Multiply accumulate (MAC) unit of said digital processor,

wherein said complex angle software instruction is part of an instruction set of said digital signal processor, and

wherein said complex angle instruction computes the phase of an input complex number by successive approximation, computing a rotated version initialized to the input complex number at a first iteration, and at iteration k rotating the rotated signal from a previous iteration to produce a new rotated input.

2. The method of claim 1 , further comprising the step of producing a magnitude of the complex number as the real part of the rotated number from a previous iteration.

3. The method of claim 1 , wherein said multiplication operations employ said one or more multipliers of said MAC unit of said digital processor.

4. The method of claim 1 , wherein said digital processor executes software instructions from program code.

5. The method of claim 1 , wherein said digital processor comprises one or more of a vector processor and a scalar processor.

6. The method of claim 5 , wherein said vector processor computes the argument of multiple complex numbers simultaneously.

7. The method of claim 1 , wherein said digital processor further comprises a polar conversion software instruction implemented using said at least one complex angle functional unit in conjunction with at least one magnitude functional unit.

8. The method of claim 1 wherein at iteration k the rotated signal is rotated by sign (k)*π*2<sup>k</sup> to produce a new rotated input, where sign (k) is opposite of the sign of the imaginary part of said rotated number at said previous iteration.

9. A digital processor that evaluates a complex angle function for an input value, x, the complex angle having a magnitude component and a phase angle component, comprising:

A memory; and

at least one hardware device, coupled to the memory, operative to:

obtain one or more complex angle software instructions having said input value, x, as an input and in response to at least one of said complex angle software instructions, performing the following:

invoke at least one complex angle functional unit that implements said one or more complex angle software instructions to apply said complex angle function to said input value, x; and

generate an output corresponding to said complex angle of said input value, x, using one or more multipliers of a Multiply Accumulate (MAC) unit of said digital processor, wherein said complex angle instruction computes the phase of an input complex number by successive approximation, computing a rotated version initialized to the input complex number at a first iteration, and at iteration k rotating said rotated signal from a previous iteration to produce a new rotated input.

10. The digital processor of claim 9 , wherein said at least one hardware device is further configured to produce a magnitude of the complex number as the real part of the rotated number from a previous iteration.

11. The digital processor of claim 9 , wherein said multiplication operations employ said one or more multipliers of said MAC unit of said digital processor.

12. The digital processor of claim 9 , wherein said digital processor executes software instructions from program code.

13. The digital processor of claim 9 , wherein said digital processor is embodied as one or more of a vector processor and a scalar processor.

14. The digital processor of claim 13 , wherein said vector processor computes the argument of multiple complex numbers simultaneously.

15. The digital processor of claim 9 , further comprising a polar conversion software instruction implemented using said at least one complex angle functional unit in conjunction with at least one magnitude functional unit.

16. The digital processor of claim 9 wherein at iteration k the rotated signal is rotated by sign (k)*π*2<sup>k</sup> to produce a new rotated input, where sign (k) is opposite of the sign of the imaginary part of said rotated number at said previous iteration.

Assignments (6)
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN CERTAIN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (032856/0031) Recorded Aug 13, 2015
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 036343/0807 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 15, 2015
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE, LTD.
To: INTEL CORPORATION
Reel/Frame 036098/0375 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
From: LSI CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035390/0388 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 17, 2014
From: AZADET, KAMERAN
To: LSI CORPORATION
Reel/Frame 032701/0824 →
Continuity (2)
Provisional Application 61812858 · Apr 17, 2013
Related Publication 20140317376A1 · Oct 23, 2014