Clock generation circuit with dual phase-locked loops
Embodiments provide a clock generation circuit with a first phase-locked loop (PLL) and a second PLL that are coupled in parallel with one another and receive a same feedback signal. The first and second PLLs generate respective output signals that are combined to generate an output clock signal. A version of the output clock signal may be passed back to the first and second PLLs as the feedback signal. In some embodiments, the second PLL may include a switch to selectively close the second PLL after the first PLL has locked. In some embodiments, the second PLL may include a bulk acoustic wave (BAW) voltage-controlled oscillator (VCO) and the first PLL may include a different type of VCO.
1. A circuit comprising:
a feedback node;
a first phase-locked loop (PLL) coupled with the feedback node, the first PLL including a first voltage-controlled oscillator (VCO) and a first feedback loop to generate a first output signal based on a feedback signal at the feedback node;
a second PLL coupled with the feedback node, the second PLL including a second VCO and a second feedback loop to generate a second output signal based on the feedback signal at the feedback node, wherein the second output signal has a higher output frequency than the first output signal;
a frequency mixer coupled with the first and second PLLs to receive the first and second output signals, respectively, and generate a clock signal at an output node based on the first and second output signals.
2. The circuit of claim 1 , further comprising a switch to close the second PLL after the first PLL has achieved lock.
3. The circuit of claim 2 , wherein the switch is to close the second PLL responsive to a lock-detect signal of the first PLL.
4. The circuit of claim 2 , wherein, prior to the switch being closed, the second VCO is to receive a control voltage corresponding substantially to a middle of a tuning range of the second VCO.
5. The circuit of claim 1 , wherein the first PLL has a higher gain than the second PLL.
6. The circuit of claim 1 , wherein the second PLL has a narrower tuning range than the first PLL.
7. The circuit of claim 1 , wherein the first and second PLLs are to generate the respective first or second output signals based further on a reference signal, and
wherein the circuit further comprises a frequency divider coupled between the frequency mixer and the feedback node to pass a frequency divided version of the clock signal to the feedback node.
8. The circuit of claim 1 , wherein the second VCO is a bulk acoustic wave (BAW) VCO.
9. The circuit of claim 8 , wherein the first VCO is an inductance-capacitance (LC) VCO.
10. A method comprising:
operating a first phase-locked loop (PLL) of a clock generation circuit;
detecting that the first PLL has locked; and
closing a second PLL responsive to the detection, wherein the first and second PLLs receive a same feedback signal and combine to form an output clock signal based on the feedback signal.
11. The method of claim 10 , wherein the first PLL includes a first voltage-controlled oscillator (VCO) and the second PLL includes a second VCO that is of a different type than the first VCO.
12. The method of claim 11 , wherein the second VCO is a bulk acoustic wave (BAW) VCO.
13. The method of claim 11 , wherein the first PLL has a higher gain than the second PLL.
14. The method of claim 11 , wherein the second PLL has a narrower tuning range than the first PLL.
15. The method of claim 11 , further comprising providing, prior to closing the second PLL, a control voltage to the second VCO corresponding substantially to a middle portion of a tuning range of the second VCO.
16. A system comprising:
a transceiver;
a clock generator coupled with the transceiver, the clock generator comprising:
a feedback node;
a first phase-locked loop (PLL) coupled with the feedback node, the first PLL including a first voltage-controlled oscillator (VCO) and a first feedback loop to generate a first output signal based on a feedback signal at the feedback node;
a second PLL coupled with the feedback node, the second PLL including a second VCO and a second feedback loop to generate a second output signal based on the feedback signal at the feedback node;
a frequency mixer coupled with the first and second PLLs to generate a clock signal at an output node based on the first and second output signals; and
control circuitry coupled with the second PLL, the control circuitry configured to:
open the second PLL and provide a pre-determined control voltage to the second VCO during an initial time period;
detect that the first PLL has locked; and
close the second PLL responsive to the detection.
17. The system of claim 16 , wherein the pre-determined control voltage corresponds substantially to a middle portion of a tuning range of the second VCO.
18. The system of claim 16 , wherein the first PLL has a higher gain than the second PLL.
19. The system of claim 16 , wherein the second PLL has a narrower tuning range than the first PLL.
20. The system of claim 16 , wherein the first and second PLLs are to generate the respective first or second output signals based further on a reference signal, and wherein the circuit further comprises a frequency divider coupled between the frequency mixer and the feedback node to pass a frequency divided version of the clock signal to the feedback node.
21. The system of claim 16 , wherein the first VCO is an inductance-capacitance (LC) VCO and the second VCO is a bulk acoustic wave (BAW) VCO.