IP Library Granted Patent US 9,178,730
Granted Patent B2
US 9,178,730 · App. 14/373,924 · Granted Nov 3, 2015

Clock distribution module, synchronous digital system and method therefor

Inventors: Michael Priel (Netanya, IL); David Dzebisashvili (Tel Aviv, IL); Leonid Fleshel (Hertzelia, IL)
Assignee: Freescale Semiconductor, Inc.
H04L25/45G06F1/10H04L25/44
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Quick Facts
Patent No.
US 9,178,730
App. No.
14/373,924
Granted
Nov 3, 2015
Kind
B2
Abstract

A clock distribution module for a digital synchronous system is described. The clock distribution module comprising a first node arranged to comprise a clock signal comprising a propagation delay relative to a reference clock signal, at least one further node arranged to comprise a clock signal comprising a propagation delay relative to the reference clock signal corresponding to that of the first node, and a clock configuration module. The clock configuration module is arranged to receive at least one indication of clock skew between the first node and at least one further node of the clock distribution module, and to selectively couple the first node to the at least one further node based at least partly on the at least one indication of clock skew there between.

Claims (63)

1. A clock distribution module for a digital synchronous system, the clock distribution module comprising:

a first node arranged to comprise a clock signal comprising a propagation delay relative to a reference clock signal;

at least one further node arranged to comprise a clock signal comprising a propagation delay relative to the reference clock signal corresponding to that of the first node; and

a clock configuration module;

wherein the clock configuration module is arranged to receive at least one indication of clock skew between the first node and at least one further node of the clock distribution module, and to selectively couple the first node to the at least one further node based at least partly on the at least one indication of clock skew there between.

2. The clock distribution module of claim 1 , wherein the clock configuration module is arranged to receive at least one indication of clock skew between the first and at least one further nodes comprising at least one from a group comprising:

an indication of a process corner of an integrated circuit device within which the clock distribution module is implemented;

an indication of a voltage supply level for at least a part of the clock distribution module;

an indication of a junction temperature for at least a part of the clock distribution module;

an indication of branch activity for the first and at least one further nodes; and

an indication of measured skew between the first and at least one further nodes.

3. The clock distribution module of claim 1 , wherein the clock configuration module is arranged to:

determine a level of skew between the first and at least one further nodes based at least partly on the received at least one indication;

compare the determined level of skew to a skew threshold level; and

selectively couple the first node to the at least one further node upon the determined level of skew being greater than the skew threshold level.

4. The clock distribution module of claim 3 , wherein the clock configuration module is further arranged to receive at least one indication of an operational characteristic for at least a part of the synchronous digital system, and determine the skew threshold level based at least partly on the received at least one indication of an operational characteristic.

5. The clock distribution module of claim 4 , wherein the clock configuration module is arranged to:

determine a lower skew threshold level upon receipt of an indication of a higher performance operating mode for the at least part of the synchronous digital system; and

determine a higher skew threshold level upon receipt of an indication of a reduced power consumption operating mode for the at least part of the synchronous digital system.

6. The clock distribution module of claim 4 , wherein the clock configuration module is arranged to:

determine a lower skew threshold level upon receipt of an indication of a higher operating frequency for the at least part of the synchronous digital system; and

determine a higher skew threshold level upon receipt of an indication of a lower operating frequency for the at least part of the synchronous digital system.

7. The clock distribution module of claim 4 , wherein the clock configuration module is arranged to:

determine a lower skew threshold level upon receipt of an indication of a lower supply voltage level for the at least part of the synchronous digital system; and

determine a higher skew threshold level upon receipt of an indication of a higher supply voltage level for the at least part of the synchronous digital system.

8. The clock distribution module of claim 1 , wherein the clock distribution module further comprises at least one switching element operably coupled between the first and at least one further node, and selectively configurable to operably couple the first node to the at least one further node.

9. The clock distribution module of claim 8 , wherein the clock configuration module being further arranged to:

selectively configure the at least one switching element to operably couple the first node to the at least one further node upon a determined level of skew between the first and at least one further nodes being greater than a skew threshold level; and

selectively configure the at least one switching element to isolate the first node from the at least one further node upon a determined level of skew between the first and at least one further nodes being less than a skew threshold level.

10. The clock distribution module of claim 1 implemented within an integrated circuit device comprising at least one die within a single integrated circuit package.

11. A synchronous digital system comprising a clock distribution module, the clock distribution module comprising:

a first node arranged to comprise a clock signal comprising a propagation delay relative to a reference clock signal;

at least one further node arranged to comprise a clock signal comprising a propagation delay relative to the reference clock signal corresponding to that of the first node; and

a clock configuration module;

wherein the clock configuration module is arranged to receive at least one indication of clock skew between the first node and at least one further node of the clock distribution module, and to selectively couple the first node to the at least one further node based at least partly on the at least one indication of clock skew there between.

12. A method of configuring a clock tree distribution network, the method comprising:

receiving at least one indication of clock skew between a first node of the clock distribution module and at least one further node of the clock distribution module; and

selectively coupling the first node to the at least one further node based at least partly on the at least one indication of clock skew there between.

13. The method of claim 12 , wherein the method comprises:

receiving at least one indication of clock skew between a first node of the clock distribution module and at least one further node of the clock distribution module;

determining a level of skew between the first and at least one further nodes based at least partly on the received at least one indication;

comparing the determined level of skew to a skew threshold level; and

selectively coupling the first node to the at least one further node upon the determined level of skew being greater than the skew threshold level.

14. The method of claim 13 , further comprising:

receiving at least one indication of an operational characteristic for at least a part of the synchronous digital system; and

determining the skew threshold level based at least partly on the received at least one indication of an operational characteristic.

15. The method of claim 14 , further comprising:

determining a lower skew threshold level upon receipt of an indication of a higher performance operating mode for the at least part of the synchronous digital system; and

determining a higher skew threshold level upon receipt of an indication of a reduced power consumption operating mode for the at least part of the synchronous digital system.

16. The method of claim 14 , further comprising:

determining a lower skew threshold level upon receipt of an indication of a higher operating frequency for the at least part of the synchronous digital system; and

determining a higher skew threshold level upon receipt of an indication of a lower operating frequency for the at least part of the synchronous digital system.

17. The synchronous digital system of claim 11 , wherein the clock configuration module is arranged to:

determine a level of skew between the first and at least one further nodes based at least partly on the received at least one indication;

compare the determined level of skew to a skew threshold level; and

selectively couple the first node to the at least one further node upon the determined level of skew being greater than the skew threshold level.

18. The synchronous digital system of claim 17 , wherein the clock configuration module is further arranged to receive at least one indication of an operational characteristic for at least a part of the synchronous digital system, and determine the skew threshold level based at least partly on the received at least one indication of an operational characteristic.

19. The synchronous digital system of claim 18 , wherein the clock configuration module is arranged to:

determine a lower skew threshold level upon receipt of an indication of a higher performance operating mode for the at least part of the synchronous digital system; and

determine a higher skew threshold level upon receipt of an indication of a reduced power consumption operating mode for the at least part of the synchronous digital system.

20. The synchronous digital system of claim 18 , wherein the clock configuration module is arranged to:

determine a lower skew threshold level upon receipt of an indication of a higher operating frequency for the at least part of the synchronous digital system; and

determine a higher skew threshold level upon receipt of an indication of a lower operating frequency for the at least part of the synchronous digital system.

Assignments (24)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042985 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042762 FRAME 0145. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051145/0184 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051030/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0387 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050745/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042762/0145 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042985/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040652 FRAME: 0241. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Jan 5, 2017
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 041260/0850 →
MERGER Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 040652/0241 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12092129 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Jul 14, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039361/0212 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
SECURITY AGREEMENT SUPPLEMENT Recorded Mar 7, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 038017/0058 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 7, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037458/0502 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 7, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037458/0460 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0921 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Nov 4, 2014
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 034153/0027 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Nov 4, 2014
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 034160/0351 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Nov 4, 2014
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 034160/0370 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 23, 2014
From: PRIEL, MICHAEL; DZEBISASHVILI, DAVID; FLESHEL, LEONID
To: FREESCALE SEMICONDUCTOR INC.
Reel/Frame 033369/0365 →
Continuity (1)
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