Granted Patent B2

US 9,436,846 · App. 14/401,149 · Granted Sep 6, 2016

Abstract

Claims (84)

1. A semiconductor device, comprising:

a plurality of on-chip processors;

a plurality of key RAMs;

a plurality of key RAM controllers;

a fuse bank, wherein the fuse bank includes a plurality of fuses;

a fuse bank controller; and

a boot controller,

wherein the boot controller is configured to:

during a first programming stage, receive a first device key for later use in a first key-protected processing by a first on-chip processor of the plurality of on-chip processors, a size of the first device key and a type of the first device key, allocate a first array of fuses in the fuse bank in dependence on the size of the first device key for storing the first device key in the fuse bank, allocate a further array of fuses of the fuse bank for storing a key directory, and control the fuse bank controller to program the first device key into the fuse bank and to register a first key information in the key directory, the first key information comprising a size and a location of the first array and the type of the first device key, and

during a boot-time, control the fuse bank controller to retrieve the first key information from the key directory in the fuse bank, control the fuse bank controller to retrieve the first device key from the fuse bank in dependence on the first key information, and provide the first device key to a first key RAM controller of the plurality of key RAM controllers, associated with a first key RAM of the plurality of key RAMs;

wherein the fuse bank controller is configured to:

during the first programming stage, receive the first key information and the first key from the boot controller, program the first array of fuses with the first device key in dependence on the first key information, and program the first key information in the key directory in the fuse bank,

during the boot-time, retrieve the first key information from the key directory under control of the boot controller, provide the first device key information to the boot controller, retrieve the first device key from the fuse bank under control of the boot controller, and provide the first device key to the boot controller, and

during a run-time, prevent access to the first device key in the fuse bank;

wherein the first key RAM controller is configured to:

during the boot-time, receive the first device key from the boot controller and store the first device key in the first key RAM, and

during the run-time, restrict access to the first device key in the first key RAM to exclusive access by the first on-chip processor; and

wherein the first on-chip processor is configured to, during the run-time, retrieve the first device key from the first key RAM and use the first device key in the first key-protected processing.

2. A semiconductor device according to claim 1 , the fuse bank comprising a first lock fuse arranged to prevent changing the first device key after the first device key has been programmed.

3. A semiconductor device according to claim 1 ,

wherein the boot controller is configured to:

during a second programming stage, receive a second device key for later use in a second key-protected processing by a second on-chip processor of the plurality of on-chip processors, a size of the second device key and a type of the second device key, allocate a second array of fuses in the fuse bank in dependence on the size of the second device key for storing the second device key in the fuse bank, and control the fuse bank controller to program the second device key into the fuse bank and to register a second key information in the key directory, the second key information comprising a size and a location of the second array and the type of the second device key, and

during the boot-time, control the fuse bank controller to retrieve the second key information from the key directory in the fuse bank, control the fuse bank controller to retrieve the second device key from the fuse bank in dependence on the second key information, and provide the second device key to a second key RAM controller of the plurality of key RAM controllers, associated with a second key RAM of the plurality of key RAMs;

wherein the fuse bank controller is configured to:

during the second programming stage, receive the second key information and the second key from the boot controller, program the second array of fuses with the second device key in dependence on the second key information, and program the second key information in the key directory in the fuse bank, and

during the boot-time, retrieve the second key information from the key directory under control of the boot controller, provide the second device key information to the boot controller, retrieve the second device key from the fuse bank under control of the boot controller, and provide the second device key to the boot controller, and

during the run-time, prevent access to the second device key in the fuse bank;

wherein the second key RAM controller is configured to:

during the boot-time, receive the second device key from the boot controller and store the second device key in the second key RAM, and

during the run-time, restrict access to the second device key in the second key RAM to exclusive access by the second on-chip processor; and

wherein the second on-chip processor is configured to, during the run-time, retrieve the second device key from the second key RAM and use the second device key in the second key-protected processing.

4. A semiconductor device according to claim 3 , the fuse bank comprising a lock fuse arranged to prevent changing the second device key after the second device key has been programmed.

5. A semiconductor device according to claim 1 , comprising a cryptographic accelerator and an array of master key fuses for storing a master key,

wherein the boot controller is configured to:

during a master key programming stage, receive a master key and control the fuse bank controller to program the master key into the array of master key fuses, and

during a second programming stage, provide a second device key to the cryptographic accelerator for encrypting the second device key with the master key from the fuse bank controller, and

during the boot-time, control the cryptographic accelerator to retrieve the second device key in encrypted form and the master key from the fuse bank controller and decrypt the second device key with the master key, and receive the second device key from the cryptographic accelerator;

wherein the fuse bank controller is configured to:

during the master key programming stage, receive the master key from the boot controller and program the master key into the array of master key fuses,

during a third programming stage, read the master key from the array of master key fuses, provide the master key to the cryptographic accelerator for encrypting the second device key provided by the boot controller with the master key, and receive the second device key in encrypted form from the cryptographic accelerator for using the second device key in encrypted form in performing the third programming stage, and

during the boot-time, after having retrieved the second device key in encrypted form, provide the second device key in encrypted form and the master key to the cryptographic accelerator for decrypting the second device key with the master key to obtain the second device key;

wherein the cryptographic accelerator is configured to:

during a fourth programming stage, receive a third device key from the boot controller and the master key from the fuse bank controller, encrypt the third device key with the master key to obtain the third device key in encrypted form, and provide the third device key in encrypted form to the fuse bank controller, and

during the boot-time, receive the third device key in encrypted form and the master key from the fuse bank controller, decrypt the third device key in encrypted form to obtain the third device key, and provide the third device key after being decrypted to the boot controller.

6. A semiconductor device according to claim 5 , the fuse bank controller configured to use the first or the second device key in encrypted form in programming the first or second device key in the fuse bank.

7. A semiconductor device according to claim 5 , configured to cooperate with an external memory comprising a plurality of non-volatile memory elements,

wherein the boot controller is configured to:

during a further programming stage, receive a further device key for later use in a further key-protected processing by a further on-chip processor of the plurality of on-chip processors, a size of the further device key and a type of the further device key, provide the further device key to the cryptographic accelerator for encrypting the further device key with the master key, receive the further device key in encrypted form from the cryptographic accelerator, allocate an array of non-volatile memory elements in the external memory in dependence on the size of the further device key in encrypted form for storing the further device key in encrypted form in the external memory, program the further device key in encrypted form into the external memory, allocate a further array of non-volatile memory elements in the external memory for storing a further key directory, register a further key information in the further key directory, the further key information comprising a size and a location of the further array and the type of the further device key, and

during the boot-time, retrieve the further key information from the further key directory from external memory, retrieve the further device key in encrypted form from the external memory in dependence on the further key information retrieved from the further key directory, provide the further device key in encrypted form to the cryptographic accelerator for decrypting the further device key with the master key, receive the further device key after being decrypted from the cryptographic accelerator, and provide the further device key to a further key RAM controller of the plurality of key RAM controllers, associated with a further key RAM of the plurality of key RAMs;

wherein the further key RAM controller is configured to:

during the boot-time, receive the further device key from the boot controller and store the further device key in the further key RAM, and

during the run-time, restrict access to the further device key in the further key RAM to exclusive access by the further on-chip processor; and

wherein the further on-chip processor is configured to, during the run-time, retrieve the further device key from the further key RAM and use the further device key in the further key-protected processing.

8. A semiconductor device according to claim 7 , the further non-volatile memory elements being further one-time programmable non-volatile memory elements, and the external memory comprising a further lock fuse arranged to prevent changing the further device key after the further device key has been programmed.

9. A semiconductor device according to claim 5 , the cryptographic accelerator being integrated in one of the first, a second or a further on-chip processor.

10. A semiconductor device according to claim 5 , the cryptographic accelerator being integrated in the boot controller or in the fuse bank controller.

11. A semiconductor device according to claim 9 , wherein at least one of the first, second and further on-chip processors comprises a multimedia interface.

12. A semiconductor device according to claim 1 , wherein at least one of the first, a second or a further on-chip processor comprises a multimedia interface, the multimedia interface being protected with a third device key obtainable from a multimedia licensing authority for forming the first, a second or a further device key respectively.

13. A semiconductor device according to claim 1 , wherein the first on-chip processor comprises a firmware update unit, the firmware update unit being protected with an advanced encryption standard (AES) key forming the first device key.

14. A semiconductor device according to claim 1 , the semiconductor device further comprising a tamper detection circuit arranged to detect external monitoring, tampering or other failure of the semiconductor device and to provide a tamper detection signal to the fuse bank controller upon such detection, the fuse bank controller being arranged to inhibit access to one or more device keys or to a master key stored in the fuse bank.

15. A semiconductor device according to claim 7 , the semiconductor device implemented in an electronic module, the electronic module comprising a memory device and the external memory, the memory device being external to the semiconductor device.

16. A semiconductor device according to claim 15 , wherein at least the first device key being programmed in the fuse bank of the semiconductor device and the further device key being programmed in encrypted form in the external memory.

17. A method of programming a semiconductor device, wherein the semiconductor device includes:

a plurality of on-chip processors;

a plurality of key RAMs;

a plurality of key RAM controllers;

a fuse bank, wherein the fuse bank includes a plurality of fuses;

a fuse bank controller; and

a boot controller,

wherein the boot controller is configured to:

during a first programming stage, receive a first device key for later use in a first key-protected processing by a first on-chip processor of the plurality of on-chip processors, a size of the first device key and a type of the first device key, allocate a first array of fuses in the fuse bank in dependence on the size of the first device key for storing the first device key in the fuse bank, allocate a further array of fuses of the fuse bank for storing a key directory, and control the fuse bank controller to program the first device key into the fuse bank and to register a first key information in the key directory, the first key information comprising a size and a location of the first array and the type of the first device key, and

during a boot-time, control the fuse bank controller to retrieve the first key information from the key directory in the fuse bank, control the fuse bank controller to retrieve the first device key from the fuse bank in dependence on the first key information, and provide the first device key to a first key RAM controller of the plurality of key RAM controllers, associated with a first key RAM of the plurality of key RAMs;

wherein the fuse bank controller is configured to:

during the first programming stage, receive the first key information and the first key from the boot controller, program the first array of fuses with the first device key in dependence on the first key information, and program the first key information in the key directory in the fuse bank,

during the boot-time, retrieve the first key information from the key directory under control of the boot controller, provide the first device key information to the boot controller, retrieve the first device key from the fuse bank under control of the boot controller, and provide the first device key to the boot controller, and

during a run-time, prevent access to the first device key in the fuse bank,

wherein the first key RAM controller is configured to:

during the boot-time, receive the first device key from the boot controller and store the first device key in the first key RAM, and

during the run-time, restrict access to the first device key in the first key RAM to exclusive access by the first on-chip processor; and

wherein the first on-chip processor is configured to, during the run-time, retrieve the first device key from the first key RAM and use the first device key in the first key-protected processing,

the method comprising:

programming, by a device manufacturer of the semiconductor device, at least the first device key in the fuse bank during the first programming stage.

18. A method according to claim 17 further comprising programming, by a manufacturer of an electronic module comprising the semiconductor device, a second device key in the fuse bank during a second programming stage.

19. A method according to claim 17 wherein the semiconductor device is configured to cooperate with an external memory, wherein a memory device includes the external memory, the memory device being external to the semiconductor device, the method further comprising programming, by a manufacturer of an electronic module comprising the semiconductor device, a further device key received during a further programming stage in the external memory in the memory device, in encrypted form, during the further programming stage.

Assignments (24)