IP Library Granted Patent US 9,501,443
Granted Patent B2
US 9,501,443 · App. 14/403,607 · Granted Nov 22, 2016

Differential line driver circuit and method therefor

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Quick Facts
Patent No.
US 9,501,443
App. No.
14/403,607
Granted
Nov 22, 2016
Kind
B2
Abstract

A differential line driver circuit comprising a plurality of driver stages is described. Each driver stage is operably coupled to at least one output of the line driver circuit and arranged to receive at least one control signal and to drive at least one output signal on the at least one output of the line driver circuit in accordance with the at least one control signal received thereby. The line driver circuit further comprises at least one delay component arranged to receive the at least one control signal, and to sequentially propagate the at least one control signal to the driver stages with time delays between the propagation of the at least one control signal to sequentially adjacent driver stages. The delay component is arranged to sequentially propagate the at least one control signal to the driver stages such that such that the at least one control signal is propagated with at least one of: a progressively increasing time delay between sequentially adjacent driver stages; and a progressively decreasing time delay between sequentially adjacent driver stages.

Claims (34)

1. A differential line driver circuit comprising:

a plurality of driver stages, each driver stage being operably coupled to two different outputs of the line driver circuit and arranged to receive at least one control signal and to drive output signals on the two different outputs of the line driver circuit in accordance with the at least one control signal received thereby;

the line driver circuit further comprises at least one delay component arranged to receive the at least one control signal, and to sequentially propagate the at least one control signal to the driver stages with time delays between the propagation of the at least one control signal to sequentially adjacent driver stages;

wherein

each of the plurality of driver stages includes a first switch, a first resistor, a second switch, and a second resistor,

the first switch of one of the plurality of driver stages is operated with the at least one control signal to couple the first resistor of the one of the plurality of driver stages to one of the different outputs, and

the second switch of the one of the plurality of driver stages is operated with the at least one control signal to couple the second resistor of the one of the plurality of driver stages to another one of the different outputs; and

the delay component is arranged to sequentially propagate the at least one control signal to the driver stages such that the at least one control signal is propagated with at least one of:

a progressively increasing time delay between sequentially adjacent driver stages; and

a progressively decreasing time delay between sequentially adjacent driver stages.

2. The differential line driver circuit of claim 1 , wherein the at least one delay component is arranged to propagate the at least one control signal to the driver stages such that an output signal of the line driver circuit comprises a substantially linear slope.

3. The differential line driver circuit of claim 2 , wherein the at least one delay component is arranged to propagate the at least one control signal to the driver stages such that the at least one control signal is propagated with delays between sequentially adjacent driver stages configured in accordance with a time delay function derived to achieve a constant derivative of an output voltage signal for the switching driver stages.

4. The differential line driver circuit of claim 1 , wherein the at least one delay component is arranged to propagate the at least one control signal to the driver stages such that:

the at least one control signal is propagated with a first set of delays; and

the at least one control signal is propagated with a different set of delays between sequentially adjacent driver stages during a falling slope of at least one of the output signals of the line driver circuit.

5. The differential line driver circuit of claim 4 , wherein the set of delays between sequentially adjacent driver stages during a falling slope of the at least one output signal of the line driver circuit is the reverse of the set of delays between sequentially adjacent driver stages during a rising slope of the at least one of the output signals of the line driver circuit.

6. The differential line driver circuit of claim 4 , wherein different time delays are configured within a respective delay block between adjacent driver stages for a rising slope and a falling slope by configuring different resistances within respective signal paths of an inverter of the delay block.

7. The differential line driver circuit of claim 1 , wherein the line driver circuit comprises a plurality of uniform driver stages.

8. The differential line driver circuit of claim 1 , wherein the line driver circuit comprises a Controller Area Network (CAN) line driver circuit.

9. The differential line driver circuit of claim 1 when implemented within an integrated circuit device comprising at least one die within a single integrated circuit package.

10. The differential line driver circuit of claim 1 , wherein the delay component includes a plurality of delay blocks, and each of the plurality of delay blocks includes a comparator component and an RC circuit operably coupled in series with the comparator component.

11. The differential line driver circuit of claim 1 , further comprising a termination resistor coupled between the different outputs.

12. The differential line driver circuit of claim 1 , wherein the delay component includes a plurality of delay blocks, and each of the plurality of delay blocks includes a pair of series inverters and an RC circuit operably coupled in series with the pair of series inverters.

13. The differential line driver circuit of claim 1 , wherein the delay component includes a plurality of delay blocks, and each of the plurality of delay blocks includes a pair of complimentary transistors.

14. A method of driving output signals for transmission over differential outputs, the method comprising:

receiving at least one control signal; and

sequentially propagating the at least one control signal to a plurality of driver stages with time delays between the propagation of the at least one control signal to sequentially adjacent driver stages, wherein each of the plurality of driver stages includes a first switch, a first resistor, a second switch, and a second resistor,

wherein the method further comprises:

operating the first switch of one of the plurality of driver stages with the at least one control signal to couple the first resistor of the one of the plurality of driver stages to one of the differential outputs;

operating the second switch of the one of the plurality of driver stages with the at least one control signal to couple the second resistor of the one of the plurality of driver stages to another one of the differential outputs;

sequentially propagating the at least one control signal to the driver stages such that:

the at least one control signal is propagated with at least one of:

a progressively increasing time delay between sequentially adjacent driver stages; and

a progressively decreasing time delay between sequentially adjacent driver stages.

Assignments (24)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042762 FRAME 0145. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051145/0184 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051030/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0387 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042985 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050745/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042762/0145 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042985/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040652 FRAME: 0241. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Jan 5, 2017
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 041260/0850 →
MERGER Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 040652/0241 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12092129 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Jul 14, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039361/0212 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
SECURITY AGREEMENT SUPPLEMENT Recorded Mar 7, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 038017/0058 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 5, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037444/0444 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 5, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037444/0535 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037358/0001 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Feb 18, 2015
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 035033/0001 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Feb 18, 2015
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 035034/0019 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Feb 18, 2015
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 035033/0923 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 25, 2014
From: PARDOEN, MATTHIJS
To: FREESCALE SEMICONDUCTOR INC.
Reel/Frame 034258/0473 →