IP Library Granted Patent US 9,438,236
Granted Patent B2
US 9,438,236 · App. 14/409,310 · Granted Sep 6, 2016

Input/output driver circuit, integrated circuit and method therefor

Inventors: Michael Priel (Netanya, IL); Dan Kuzmin (Givat Shmuel, IL); Sergey Sofer (Rishon Lezion, IL)
Assignee: FREESCALE SEMICONDUCTOR, INC.
H03K19/017509H03K19/00384H03K19/018521
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Quick Facts
Patent No.
US 9,438,236
App. No.
14/409,310
Granted
Sep 6, 2016
Kind
B2
Abstract

An input/output (IO) driver circuit is described. The IO buffer driver circuit comprises: at least one input for receiving an input signal and at least one output for providing at least one output signal; and a plurality of switches arranged to provide a variable voltage level between a low voltage value and a high voltage value to the at least one output. The at least one first switch of the plurality of switches is arranged to initiate a voltage change to an intermediate voltage level between the low voltage value and the high voltage value in a first time period. The at least one second switch of the plurality of switches is arranged to continue the voltage change to the low voltage value or the high voltage value in a second time period.

Claims (32)

1. An input/output (IO) driver circuit comprising:

at least one input for receiving an input signal and at least one output for providing at least one output signal;

a plurality of switches arranged to provide a variable voltage level between a low voltage value and a high voltage value to the at least one output, wherein

at least one first switch of the plurality of switches is arranged to initiate a voltage change to an intermediate voltage level between the low voltage value and the high voltage value in a first time period, wherein the voltage change to the intermediate voltage level is an increasing voltage change that is followed by a decreasing voltage change to a second different intermediate voltage level, and

at least one second switch of the plurality of switches is arranged to continue the voltage change to the low voltage value or the high voltage value in a second time period.

2. The I/O driver circuit of claim 1 wherein the plurality of switches comprises two sets of switches such that the at least one first switch and the at least one second switch of the plurality of switches form at least part of a first set of switches that is turned ‘on’ whilst a second set of switches is turned ‘off’.

3. The I/O driver circuit of claim 2 wherein the first set of switches is arranged to initiate a voltage increase to the intermediate voltage level through turning ‘on’ of the at least one first switch and thereafter to continue the voltage change to the high voltage value through turning ‘on’ of the at least one second switch.

4. The I/O driver circuit of claim 3 wherein the second set of switches is arranged to initiate a voltage decrease to an intermediate voltage level and thereafter to continue the voltage change to the low voltage value.

5. The I/O driver circuit of claim 1 wherein the at least one first switch is either a weak pull-up switch or a weak pull-down switch that is driven on less hard than a respective at least one pull-up second switch or pull-down second switch.

6. The I/O driver circuit of claim 1 wherein the at least one first switch is arranged to initiate the voltage change to the intermediate voltage level that resides in a vicinity of a threshold voltage level.

7. The I/O driver circuit of claim 1 wherein the first time period is different to the second time period.

8. The I/O driver circuit of claim 1 wherein the first time period does not overlap the second time period.

9. The I/O driver circuit of claim 1 wherein the first time period overlaps the second time period.

10. The I/O driver circuit of claim 1 further comprising a control circuit operably coupled to a timer circuit arranged to ensure that at least one of the following conditions exist: that the first time period is different to the second time period, that the first time period does not overlap the second time period.

11. The I/O driver circuit of claim 1 wherein the plurality of switches comprise a plurality of transistors arranged to enable timing controllable termination of the I/O driver circuit.

12. An integrated circuit comprising the I/O driver circuit of claim 1 .

13. An input/output (IO) driver circuit comprising:

at least one input for receiving an input signal and at least one output for providing at least one output signal; and

a plurality of switches arranged to provide a variable voltage level between a low voltage value and a high voltage value to the at least one output, wherein

a first switch of the plurality of switches is arranged to initiate a voltage change to a first intermediate voltage level in a first intermediate time period,

a second switch of the plurality of switches is arranged to initiate a voltage change to a second intermediate voltage level in a second intermediate time period, and

at least one third switch of the plurality of switches is arranged to continue the voltage change to the low voltage value or the high voltage value in a third intermediate time period.

14. The I/O driver circuit of claim 13 wherein the first switch is either a weak pull-up switch or a weak pull-down switch that is driven on less hard than a respective pull-up second switch or pull-down second switch.

15. The I/O driver circuit of claim 13 wherein the first switch is arranged to initiate the voltage change to the first intermediate voltage level that resides in a vicinity of a threshold voltage level.

16. A method of providing an output for an input/output driver circuit comprising a plurality of switches arranged to provide a variable voltage level between a low voltage value and a high voltage value, the method comprising:

applying a first variable input signal to at least one first switch of the plurality of switches thereby initiating a voltage change output from the input/output driver circuit to a first intermediate voltage level between the low voltage value and the high voltage value in a first time period;

applying a second variable input signal to at least one second switch of the plurality of switches thereby continuing the voltage change in a second time period;

applying a third variable input signal to at least one third switch of the plurality of switches thereby initiating a voltage change to a second intermediate voltage level in a second intermediate time period prior to applying the second variable input signal to the at least one second switch; and

outputting the low voltage value or the high voltage value from the input/output driver circuit.

17. The method of claim 16 wherein the voltage change to an intermediate voltage level comprising:

initiating an increasing voltage change that is followed by a decreasing voltage change to a second different intermediate voltage level.

18. The method of claim 16 wherein the at least one first switch is either a weak pull-up switch or a weak pull-down switch that is driven on less hard than a respective at least one pull-up second switch or pull-down second switch.

Assignments (24)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042985 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042762 FRAME 0145. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051145/0184 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051030/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0387 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050745/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042762/0145 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042985/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040652 FRAME: 0241. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Jan 5, 2017
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 041260/0850 →
MERGER Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 040652/0241 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12092129 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Jul 14, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039361/0212 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
SECURITY AGREEMENT SUPPLEMENT Recorded Mar 7, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 038017/0058 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 5, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037444/0535 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 5, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037444/0444 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037358/0001 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Feb 18, 2015
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 035033/0001 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Feb 18, 2015
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 035033/0923 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Feb 18, 2015
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 035034/0019 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 18, 2014
From: PRIEL, MICHAEL; KUZMIN, DAN; SOFER, SERGEY
To: FREESCALE SEMICONDUCTOR INC.
Reel/Frame 034549/0642 →
Continuity (1)
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