IP Library Granted Patent US 9,434,602
Granted Patent B2
US 9,434,602 · App. 14/446,910 · Granted Sep 6, 2016

Reducing MEMS stiction by deposition of nanoclusters

Inventors: Robert F. Steimle (Austin, TX); Ruben B. Montez (Cedar Park, TX)
Assignee: Freescale Semiconductor, Inc.
B81B3/001B81B2201/0235B81B2203/0181
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Quick Facts
Patent No.
US 9,434,602
App. No.
14/446,910
Granted
Sep 6, 2016
Kind
B2
Abstract

Certain microelectromechanical systems (MEMS) devices, and methods of creating them, are disclosed. The method may include forming a structural layer over a substrate; forming a mask layer over the structural layer, wherein the mask layer is formed with a material selective to an etching process; forming a plurality of nanoclusters on the mask layer; and etching the structural layer using at least the etching process.

Claims (38)

1. A method for manufacturing a microelectromechanical systems (MEMS) device, the method comprising:

forming a structural layer over a substrate;

forming a mask layer over the structural layer, wherein the mask layer is formed with a material selective to an etching process;

forming a plurality of nanoclusters on the mask layer;

using the nanoclusters as a mask for removing portions of the mask layer; and

etching the structural layer using remaining portions of the mask layer as a mask for the etching of the structural layer forming a plurality of surface roughness features on a travel stop of the MEMS device.

2. The method of claim 1 , wherein the etching process comprises:

a first etching process for the removing portions of the mask layer; and

a second etching process operable to etch the structural layer.

3. The method of claim 2 , wherein performing the second etching process further comprises removing the plurality of nanoclusters.

4. The method of claim 1 , wherein the etching process comprises an anisotropic etch.

5. The method of claim 1 , wherein the etching process comprises an isotropic etch.

6. The method of claim 1 , further comprises:

forming a sacrificial layer on the etched structural layer; and

forming a second structural layer over the sacrificial layer.

7. The method of claim 6 , further comprising planarizing a portion of the sacrificial layer prior to forming the second structural layer.

8. The method of claim 1 , wherein a nanocluster comprises one of silicon carbide, silicon germanium, polysilicon, silicon, or germanium, wherein the nanocluster is one of the plurality of nanoclusters.

9. The method of claim 1 , wherein the structural layer comprises a polysilicon layer.

10. The method of claim 1 , wherein the material selective to the etching process comprises a silicon oxide.

11. A method for manufacturing a microelectromechanical systems (MEMS) device, the method comprising:

forming a structural layer over a substrate;

forming a mask layer over the structural layer;

forming a plurality of nanoclusters on the mask layer;

using the nanoclusters as a mask for removing portions of the mask layer; and

etching the structural layer using remaining portions of the mask layer as a mask for the etching of the structural layer forming a plurality of surface roughness features of a travel stop feature of the MEMS device; and

forming a movable body, wherein the structural layer forms a fixed surface having a portion facing a major surface of the movable body, and the fixed surface is operable to contact at least a portion of the plurality of surface roughness features.

12. The method of claim 11 , further comprising:

forming a sacrificial layer on the etched structural layer; and

forming a second structural layer over the sacrificial layer.

13. The method of claim 11 , wherein the movable body comprises:

a pivoting proof mass of a teeter-totter accelerometer;

the travel stop feature is configured to contact the structural layer to prevent over rotation of the pivoting proof mass, and comprises a portion of the major surface facing the fixed surface.

14. The method of claim 13 , wherein:

a portion of the travel stop feature is formed using a process comprising:

forming a sacrificial layer on the etched structural layer; and

forming a second structural layer over the sacrificial layer.

15. The method of claim 14 , wherein the portion of the travel stop feature is formed using a process further comprising planarizing a portion of the sacrificial layer prior to forming the second structural layer.

16. The method of claim 11 , wherein the plurality of nanoclusters are formed of one of silicon carbide, silicon germanium, polysilicon, silicon, or germanium.

Assignments (15)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040652 FRAME: 0241. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Jan 5, 2017
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 041260/0850 →
MERGER Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 040652/0241 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 7, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037458/0460 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 7, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037458/0502 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0921 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Nov 4, 2014
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 034160/0351 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Nov 4, 2014
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 034160/0370 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Nov 4, 2014
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 034153/0027 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 30, 2014
From: STEIMLE, ROBERT F.; MONTEZ, RUBEN B.
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 033424/0083 →
Continuity (1)
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