Digital alloy layer in a III-nitrade based heterojunction field effect transistor
View Patent ↗Embodiments include apparatuses and methods related to an HFET. In embodiments, one or all of the buffer layer, the back-barrier layer, or the barrier layer may be formed of a digital alloy. In embodiments, the digital alloy may include alternating layers of alloys of aluminum, gallium, and nitrogen. Other embodiments may be disclosed or claimed herein.
1. An apparatus comprising:
a buffer layer;
a channel layer directly coupled with the buffer layer;
a digital alloy barrier layer directly coupled with the channel layer opposite the buffer layer, wherein the digital alloy barrier layer includes at least a first and a second aluminum nitride (AlN) layer that alternates between at least a first and a second gallium nitride (GaN) layer such that the first AlN layer is between the first and the second GaN layers, and the first GaN layer is between the first and the second AlN layers; and
a cap layer directly coupled with the digital alloy barrier layer opposite the channel layer.
2. The apparatus of claim 1 , wherein both the first and second GaN layers have a first thickness, and both the first and second AlN layers have a second thickness.
3. The apparatus of claim 1 , wherein the first GaN layer has a first thickness and the second GaN layer has a second thickness that is different than the first thickness, and the first AlN layer has a third thickness and the second AlN layer has a fourth thickness that is different than the third thickness.
4. The apparatus of claim 1 , wherein the cap layer includes GaN, AlN, or silicon nitride (SiNx).
5. The apparatus of claim 1 , wherein the digital alloy barrier layer has a sheet carrier concentration that is greater than approximately 1×10 13 cm −2 .
6. The apparatus of claim 1 , wherein the channel layer includes GaN, indium gallium nitride (InGaN), or aluminum gallium nitride (AlGaN).
7. The apparatus of claim 1 , wherein the buffer layer includes GaN, an alloy back-barrier, or a digital alloy back-barrier.
8. The apparatus of claim 1 , wherein the apparatus is a heterojunction field effect transistor (HFET).
9. An apparatus comprising:
a barrier layer;
a channel layer directly coupled with the barrier layer; and
a digital alloy layer directly coupled with the channel layer opposite the barrier layer, wherein the digital alloy layer includes at least a first layer with first relative concentrations of aluminum, gallium, and nitrogen, a second layer with second relative concentrations of aluminum, gallium, and nitrogen, a third layer with third relative concentrations of aluminum, gallium, and nitrogen, and a fourth layer with fourth relative concentrations of aluminum, gallium, and nitrogen, wherein the first relative concentration is different from the second relative concentration and the fourth relative concentration, and the third relative concentration is different than the second relative concentration and the fourth relative concentration.
10. The apparatus of claim 9 , wherein the first and third layer include aluminum nitride (AlN).
11. The apparatus of claim 9 , wherein the second and fourth layer include gallium nitride (GaN).
12. The apparatus of claim 9 , wherein the first relative concentration and the third relative concentration are the same as each other, and the second relative concentration and the fourth relative concentration are the same as each other.
13. The apparatus of claim 9 , wherein the digital alloy layer is a buffer layer.
14. The apparatus of claim 9 , wherein the digital alloy layer is a back-barrier layer.
15. The apparatus of claim 9 , wherein the first layer and the third layer have a same thickness as one another, and the second layer and the fourth layer have a same thickness as one another.
16. The apparatus of claim 9 , wherein the digital alloy layer has an aluminum concentration that is greater than approximately 0%.
17. The apparatus of claim 9 , further comprising a cap layer directly coupled with the barrier layer opposite the channel layer.
18. The apparatus of claim 9 , wherein the apparatus is a heterojunction field effect transistor (HFET).
19. The apparatus of claim 9 , wherein the channel layer includes a gallium nitride (GaN) based channel.
20. The apparatus of claim 9 , wherein the barrier layer includes aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), aluminum gallium indium nitride (AlGaInN), or a digital alloy.