IP Library Granted Patent US 9,461,639
Granted Patent B2
US 9,461,639 · App. 14/556,365 · Granted Oct 4, 2016

Semiconductor device and power circuit including a sense transistor for current sensing

Inventors: Christelle Franchini (Fontenilles, FR); Murielle Delage (Fonsorbes, FR); Alexis Nathanaël Huot-Marchand (Fonsorbes, FR)
Assignee: Freescale Semiconductor, Inc.
H03K17/687H01L21/823418H01L25/16H01L27/0266H01L27/088H01L29/0642H01L29/78H01L29/7817H01L29/7826G05F1/565G05F3/02H01L2924/0002H02M3/156H03K2217/0027
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Quick Facts
Patent No.
US 9,461,639
App. No.
14/556,365
Granted
Oct 4, 2016
Kind
B2
Abstract

A semiconductor device comprises a power transistor and a sense transistor. The power transistor conducts a power transistor current. The sense transistor conducts a sense transistor current substantially proportional to of the power transistor current. The power transistor and the sense transistor have drain source and a gate terminals, of which those of the sense transistor are arranged to be biased to those of the power transistor, respectively. The power transistor and the sense transistor each comprise: an inner region of type P−; an N-type buried layer; an N-type isolating barrier surrounding the inner region partially; an N-type source region in the inner region; an N-type drain region in the inner region. A barrier-to-drain connector connects the isolating barrier to the drain region, the one of the sense transistor has an electrical resistance which is higher than the resistance of the barrier-to-drain connector of the power transistor.

Claims (26)

1. A semiconductor device comprising a power transistor and a sense transistor, wherein

the power transistor is arranged to conduct a power transistor current;

the sense transistor is arranged to conduct a sense transistor current that is substantially proportional to the power transistor current;

each of the power transistor and the sense transistor is a metal-oxide semiconductor field effect transistor, MOSFET, having a drain terminal, a source terminal, and a gate terminal;

the drain terminal, the source terminal, and the gate terminal of the sense transistor are arranged to be biased to the drain potential, the source potential, and the gate potential of the power transistor, respectively;

wherein the power transistor and the sense transistor each comprise:

an inner region of type P−;

an N-type buried layer;

an N-type isolating barrier, the isolating barrier surrounding the inner region at least partially;

an N-type source region in the inner region;

an N-type drain region in the inner region; and

a barrier-to-drain connector which connects the isolating barrier to the drain region;

wherein the barrier-to-drain connector of the sense transistor has an electrical resistance which is higher than the resistance of the barrier-to-drain connector of the power transistor.

2. The semiconductor device of claim 1 , wherein the barrier-to-drain connector of the sense transistor comprises a resistor.

3. The semiconductor device of claim 2 , wherein the resistor is a surface mounted device.

4. The semiconductor device of claim 1 , comprising a die which comprises at least part of the power transistor and at least part of the sense transistor.

5. The semiconductor device of claim 4 , wherein at least part of the barrier-to-drain connector traverses a region of the die.

6. The semiconductor device of claim 4 , wherein the power transistor and the sense transistor are located adjacent to each other.

7. The semiconductor device of claim 1 , wherein the die area occupied by the power transistor is at least five times greater than the die area occupied by the sense transistor.

8. The semiconductor device of claim 1 , wherein the power transistor and the sense transistor each comprise a horizontal diode between the source region and the drain region.

9. The semiconductor device of claim 1 , wherein the power transistor and the sense transistor each comprise a vertical diode between the source region and the buried layer.

10. The semiconductor device of claim 1 , wherein the power transistor and the sense transistor each comprise a horizontal diode between the source region and the isolating barrier.

11. The semiconductor device of claim 1 , wherein the power transistor and the sense transistor are similar in structure.

12. A power circuit comprising a semiconductor device of claim 1 and a load, wherein the load is connected or connectable in parallel with the power transistor.

13. The power circuit of claim 12 , wherein the load is an inductive load and the power transistor is connectable in series with the load to form a recirculation path.

14. The power circuit of claim 12 , comprising a feedback loop arranged to control the power switch in dependence of the sense transistor current.

Assignments (20)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042762 FRAME 0145. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051145/0184 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051030/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0387 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042985 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050745/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042762/0145 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042985/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040652 FRAME: 0241. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Jan 5, 2017
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 041260/0850 →
MERGER Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 040652/0241 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12092129 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Jul 14, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039361/0212 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
SECURITY AGREEMENT SUPPLEMENT Recorded Mar 7, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 038017/0058 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 5, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037444/0535 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 5, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037444/0444 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037358/0001 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Feb 18, 2015
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 035033/0001 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Feb 18, 2015
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 035033/0923 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Feb 18, 2015
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 035034/0019 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 1, 2014
From: FRANCHINI, CHRISTELLE; DELAGE, MURIELLE; HUOT-MARCHAND, ALEXIS NATHANAËL
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 034285/0085 →
Priority Claims (1)
WO PCT/IB2014/001072 · May 16, 2014 · international
Continuity (1)
Related Publication 20150341029A1 · Nov 26, 2015