IP Library Granted Patent US 9,350,316
Granted Patent B1
US 9,350,316 · App. 14/574,008 · Granted May 24, 2016

Wideband baluns and methods of their manufacture

Inventors: James B. Krehbiel (Tempe, AZ); Abdulrhman M. S Ahmed (Gilbert, AZ); Joseph Staudinger (Gilbert, AZ)
Assignee: FREESCALE SEMICONDUCTOR, INC.
H03H7/42H01F5/003H01F41/04H03F3/19H03F3/217H03H3/00H03F2200/06H03F2200/451
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Quick Facts
Patent No.
US 9,350,316
App. No.
14/574,008
Granted
May 24, 2016
Kind
B1
Abstract

A balun structure comprises an unbalanced input terminal, a first planar coil connected to the unbalanced input terminal, a second planar coil connected to the first planar coil, a third planar coil stacked in relation to the first planar coil, a first balanced output terminal connected to the third planar coil, a fourth planar coil stacked in relation to the second planar coil, and a second balanced output terminal connected to the fourth planar coil, wherein a first length of the first planar coil and a third length of the third planar coil differ by one twelfth to one twentieth of an operational wavelength and a second length of the second planar coil and a fourth length of the fourth planar coil differ by one twelfth to one twentieth of the operational wavelength.

Claims (51)

1. A balun structure comprising:

an unbalanced input terminal;

a first planar coil coupled to the unbalanced input terminal;

a second planar coil coupled to the first planar coil;

a third planar coil stacked in relation to the first planar coil;

a first balanced output terminal coupled to the third planar coil;

a fourth planar coil stacked in relation to the second planar coil; and

a second balanced output terminal coupled to the fourth planar coil, wherein a first length of the first planar coil and a third length of the third planar coil differ by one twelfth to one twentieth of an operational wavelength and a second length of the second planar coil and a fourth length of the fourth planar coil differ by one twelfth to one twentieth of the operational wavelength.

2. The balun structure of claim 1 wherein the first length of the first planar coil and the third length of the third planar coil differ by one fourteenth to one eighteenth of the operational wavelength and the second length of the second planar coil and the fourth length of the fourth planar coil differ by one fourteenth to one eighteenth of the operational wavelength.

3. The balun structure of claim 1 having an operational bandwidth expressed as a ratio of between three to one and seven to one of a highest operational frequency to a lowest operational frequency.

4. The balun structure of claim 1 further comprising:

a direct current (DC) bias input coupled to ends of the third planar coil and the fourth planar coil opposite the first balanced output terminal and the second balanced output terminal, respectively.

5. The balun structure of claim 1 further comprising:

a first matching capacitor situated within an interior of the third planar coil and coupled to an end of the third planar coil opposite the first balanced output terminal; and

a second matching capacitor situated within an interior of the fourth planar coil and coupled to an end of the fourth planar coil opposite the second balanced output terminal.

6. The balun structure of claim 1 wherein the balun structure is embedded within an integrated circuit package and implemented on a multi-layer interposer structure underlying an integrated circuit die and overlying external interconnect terminals of the integrated circuit package.

7. The balun structure of claim 1 wherein an input end of the first planar coil is diametrically opposite a distal end of third planar coil distal with respect to the first balanced output terminal and a terminal end of the second planar coil is diametrically opposite a distal end of the fourth planar coil distal with respect to the second balanced output terminal.

8. A method of manufacture comprising:

defining, in a plurality of interconnected conductive layers separated by dielectric layers, a balun structure having an unbalanced input terminal, a first planar coil coupled to the unbalanced input terminal, a second planar coil coupled to the first planar coil, a third planar coil stacked in relation to the first planar coil, a first balanced output terminal coupled to the third planar coil, a fourth planar coil stacked in relation to the second planar coil, and a second balanced output terminal coupled to the fourth planar coil, wherein a first length of the first planar coil and a third length of the third planar coil differ by one twelfth to one twentieth of an operational wavelength and a second length of the second planar coil and a fourth length of the fourth planar coil differ by one twelfth to one twentieth of the operational wavelength.

9. The method of claim 8 wherein the defining further comprises:

establishing the first length of the first planar coil and the third length of the third planar coil to differ by one fourteenth to one eighteenth of the operational wavelength; and

establishing the second length of the second planar coil and the fourth length of the fourth planar coil to differ by one fourteenth to one eighteenth of the operational wavelength.

10. The method of claim 8 wherein the defining further comprises:

configuring the balun structure to have an operational bandwidth expressed as a ratio of between three to one and seven to one of a highest operational frequency to a lowest operational frequency.

11. The method of claim 8 further comprising:

providing a direct current (DC) bias input coupled to ends of the third planar coil and the fourth planar coil opposite the first balanced output terminal and the second balanced output terminal, respectively.

12. The method of claim 8 further comprising:

installing a first matching capacitor situated within an interior of the third planar coil and coupled to an end of the third planar coil opposite the first balanced output terminal; and

installing a second matching capacitor situated within an interior of the fourth planar coil and coupled to an end of the fourth planar coil opposite the second balanced output terminal.

13. The method of claim 8 further comprising:

embedding the balun structure within an integrated circuit package, wherein the plurality of interconnected conductive layers underlie an integrated circuit die and overlie external interconnect terminals of the integrated circuit package.

14. The method of claim 8 wherein the defining further comprises:

establishing an input end of the first planar coil to be diametrically opposite a distal end of third planar coil distal with respect to the first balanced output terminal; and

establishing a terminal end of the second planar coil to be diametrically opposite a distal end of the fourth planar coil distal with respect to the second balanced output terminal.

15. A system comprising:

a radio frequency (RF) power amplifier (PA); and

a balun structure coupled to the RF PA, the balun structure comprising:

an unbalanced input terminal;

a first planar coil coupled to the unbalanced input terminal;

a second planar coil coupled to the first planar coil;

a third planar coil stacked in relation to the first planar coil;

a first balanced output terminal coupled to the third planar coil;

a fourth planar coil stacked in relation to the second planar coil; and

a second balanced output terminal coupled to the fourth planar coil, wherein a first length of the first planar coil and a third length of the third planar coil differ by one twelfth to one twentieth of an operational wavelength and a second length of the second planar coil and a fourth length of the fourth planar coil differ by one twelfth to one twentieth of the operational wavelength.

16. The system of claim 15 wherein the RF PA is a switched mode power amplifier (SMPA).

17. The system of claim 15 wherein the balun structure further comprises a direct current (DC) bias input coupled to ends of the third planar coil and the fourth planar coil opposite the first balanced output terminal and the second balanced output terminal, respectively.

18. The system of claim 15 further comprising:

a first matching capacitor situated within an interior of the third planar coil and coupled to an end of the third planar coil opposite the first balanced output terminal; and

a second matching capacitor situated within an interior of the fourth planar coil and coupled to an end of the fourth planar coil opposite the second balanced output terminal.

19. The system of claim 15 wherein the RF PA and the balun structure are embedded within an integrated circuit package with the balun structure implemented on a multi-layer interposer structure underlying the RF PA and overlying external interconnect terminals of the integrated circuit package.

20. The system of claim 15 wherein an input end of the first planar coil is diametrically opposite a distal end of third planar coil distal with respect to the first balanced output terminal and a terminal end of the second planar coil is diametrically opposite a distal end of the fourth planar coil distal with respect to the second balanced output terminal.

Assignments (15)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040652 FRAME: 0241. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Jan 5, 2017
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 041260/0850 →
MERGER Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 040652/0241 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 5, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037444/0444 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 5, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037444/0535 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037358/0001 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Feb 18, 2015
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 035033/0001 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Feb 18, 2015
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 035034/0019 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Feb 18, 2015
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 035033/0923 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2014
From: KREHBIEL, JAMES B.; AHMED, ABDULRHMAN M. S; STAUDINGER, JOSEPH
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 034533/0107 →