IP Library Granted Patent US 9,792,803
Granted Patent B2
US 9,792,803 · App. 14/582,341 · Granted Oct 17, 2017

Secure PIN entry device

Inventors: John Henry Barrowman (Knoxville, TN); Douglas L. Manchester (Rocklin, CA)
Assignee: VeriFone, Inc.
G08B21/18G06F21/83
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Quick Facts
Patent No.
US 9,792,803
App. No.
14/582,341
Granted
Oct 17, 2017
Kind
B2
Abstract

A secure PIN entry device including a PIN entry assembly operative to receive a PIN from a user, a PIN entry prompter operative when actuated to prompt a user to enter a PIN via the PIN entry assembly, a PIN entry prompt security check enabled controller operative to prevent operation of the PIN entry prompter unless a predetermined security check has been successfully completed and security check functionality operative to check at least part of the PIN entry device for the presence of an unauthorized PIN eavesdropping element thereat and to provide an output to the PIN entry prompt security check enabled controller indicating whether the predetermined security check has been successfully completed.

Claims (43)

1. A security check system operative to check at least part of a data entry device for the presence of an unauthorized data eavesdropping element threat, said system comprising:

an electric field generator for simultaneously generating an electromagnetic field at a first multiplicity of locations in said data entry device; and

mutual capacitance sensing circuitry for sensing mutual capacitance between at least some of said first multiplicity of locations and at least a second multiplicity of locations resulting from said electromagnetic field at each of said first multiplicity of locations, said mutual capacitance sensing circuitry being operative to check at least part of the data entry device for the presence of an unauthorized data eavesdropping element threat in a key entry detection mode using autotuning functionality and in a security scan mode when the autotuning functionality is disabled.

2. The security check system according to claim 1 and wherein at least some of said first multiplicity of locations are identical to at least some of said second multiplicity of locations.

3. The security check system according to claim 1 and wherein said mutual capacitance sensing circuitry is operative in said security scan mode to measure capacitance of elements of said device and compare said capacitance with a baseline capacitance corrected for at least one environmental factor.

4. The security check system according to claim 1 and wherein said mutual capacitance sensing circuitry when operative in said security scan mode, combines changes in sensed mutual capacitance of a plurality of elements of said data entry device which exceed a predetermined threshold in order to ascertain whether a bug is present.

5. The security check system according to claim 1 and also comprising a controller operative, in the event of discovery of a bug, to provide an output alarm and disable one or more functions of said data entry device.

6. The security check system according to claim 1 and wherein said mutual capacitance sensing circuitry is operative to:

apply a signal to at least some of said first multiplicity of locations in said data entry device;

receive signals from at least some of said second multiplicity of locations; and

calculate a difference value for each of said at least some of said second multiplicity of locations vis-à-vis a suitably temperature corrected baseline for each of said at least some of said second multiplicity of locations.

7. The security check system according to claim 6 and wherein said mutual capacitance sensing circuitry is also operative to compare a sum of the absolute values of said difference values with a suitable threshold.

8. The security check system according to claim 1 and wherein said mutual capacitance sensing circuitry is operative to:

apply a signal to at least some of said first multiplicity of locations;

receive signals from at least others of said first multiplicity of locations; and

calculate a difference value for each of said others of said first multiplicity of locations vis-à-vis a suitably temperature corrected baseline for each of said others of said first multiplicity of locations.

9. The security check system according to claim 8 and wherein said mutual capacitance sensing circuitry is also operative to compare a sum of the absolute values of said difference values with a suitable threshold.

10. The security check system according to claim 1 and wherein said mutual capacitance sensing circuitry is operative to:

simultaneously apply a signal to at least some of said second multiplicity of locations;

receive signals from at least some of said first multiplicity of locations; and

calculate a difference value for each of said some of said first multiplicity of locations vis-à-vis a suitably temperature corrected baseline for each of the some of said first multiplicity of locations.

11. The security check system according to claim 10 and wherein said mutual capacitance sensing circuitry is also operative to compare a sum of the absolute values of said difference values with a suitable threshold.

12. A security check method for checking at least part of a data entry device for the presence of an unauthorized data eavesdropping element threat, said method comprising:

simultaneously generating an electromagnetic field at a first multiplicity of locations in said data entry device; and

sensing mutual capacitance between at least some of said first multiplicity of locations and at least a second multiplicity of locations resulting from said electromagnetic field at each of said first multiplicity of locations, said sensing mutual capacitance being operative to check at least part of the data entry device for the presence of an unauthorized data eavesdropping element threat in a key entry detection mode using autotuning functionality and in a security scan mode when the autotuning functionality is disabled.

13. The security check method according to claim 12 and wherein at least some of said first multiplicity of locations are identical to at least some of said second multiplicity of locations.

14. The security check method according to claim 12 and wherein said sensing mutual capacitance in said security scan mode comprises:

measuring capacitance of elements of said data entry device; and

comparing said capacitance with a baseline capacitance corrected for at least one environmental factor.

15. The security check method according to claim 12 and wherein said sensing mutual capacitance in a security scan mode comprises combining changes in sensed capacitance of a plurality of elements of said data entry device which exceed a predetermined threshold in order to ascertain whether a bug is present.

16. The security check method according to claim 12 and also comprising, in the event of discovery of a bug, at least one of providing an output alarm and disabling one or more functions of said data entry device.

17. The security check method according to claim 12 and wherein said sensing mutual capacitance comprises:

applying a signal to at least some of said first multiplicity of locations in said data entry device;

receiving signals from at least some of said second multiplicity of locations; and

calculating a difference value for each of said at least some of said second multiplicity of locations vis-à-vis a suitably temperature corrected baseline for each of said at least some of said second multiplicity of locations.

18. The security check method according to claim 12 and wherein said sensing mutual capacitance comprises:

applying a signal to at least some of said first multiplicity of locations;

receiving signals from at least others of said first multiplicity of locations; and

calculating a difference value for each of said others of said first multiplicity of locations vis-à-vis a suitably temperature corrected baseline for each of said others of said first multiplicity of locations.

19. The security check method according to claim 12 and wherein said sensing mutual capacitance comprises:

simultaneously applying a signal to at least some of said second multiplicity of locations;

receiving signals from at least some of said first multiplicity of locations; and

calculating a difference value for each of said some of said first multiplicity of locations vis-à-vis a suitably temperature corrected baseline for each of said some of said first multiplicity of locations.

Assignments (7)
ASSIGNMENT OF SECURITY INTEREST IN PATENT COLLATERAL RECORDED AT R/F 046920-0784 Recorded Apr 28, 2025
From: UBS AG, STAMFORD BRANCH, AS SUCCESSOR TO CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH, AS ASSIGNOR
To: BARCLAYS BANK PLC, AS ASSIGNEE
Reel/Frame 071095/0667 →
RELEASE OF SECURITY INTEREST RECORDED AT REEL/FRAME 46920/0817 Recorded May 10, 2019
From: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH
To: VERIFONE SYSTEMS, INC.; VERIFONE, INC.; HYPERCOM CORPORATION
Reel/Frame 049150/0190 →
SECOND LIEN PATENT SECURITY AGREEMENT Recorded Aug 23, 2018
From: VERIFONE, INC.; HYPERCOM CORPORATION
To: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH AS COLLATERAL AGENT
Reel/Frame 046920/0817 →
FIRST LIEN PATENT SECURITY AGREEMENT Recorded Aug 23, 2018
From: VERIFONE, INC.; HYPERCOM CORPORATION
To: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH AS COLLATERAL AGENT
Reel/Frame 046920/0784 →
RELEASE (R045575F0019) Recorded Aug 21, 2018
From: JPMORGAN CHASE BANK, N.A.
To: VERIFONE, INC.; HYPERCOM CORPORATION
Reel/Frame 046865/0270 →
SECURITY INTEREST Recorded Mar 13, 2018
From: VERIFONE, INC.; HYPERCOM CORPORATION
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 045575/0019 →
CHANGE OF ADDRESS Recorded May 30, 2016
From: VERIFONE, INC.
To: VERIFONE, INC.
Reel/Frame 038845/0718 →
Continuity (3)
Continuation 14088756 · Nov 25, 2013
Continuation 12985898 · Jan 6, 2011
Related Publication 20150116115A1 · Apr 30, 2015