Contact arrangements for stackable microelectronic package structures with multiple ranks
An apparatus relates generally to a microelectronic assembly. In this apparatus, a first substrate and a second substrate each have opposing surfaces. Contact arrangements are disposed on a surface of the first substrate, including: first contacts disposed as a ring to provide a first array of the contact arrangements on such surface; and second contacts disposed interior to the ring of the first contacts to provide a second array of the contact arrangements on the first surface. The first contacts and the second contacts are for interconnection with first microelectronic dies and second microelectronic dies. The second microelectronic dies are disposed below the first microelectronic dies in same a package as the first microelectronic dies. The first microelectronic dies and the second microelectronic dies include at least two ranks thereof for commonly sharing the first contacts and the second contacts among the first microelectronic dies and the second microelectronic dies.
1. A microelectronic assembly, comprising:
a first substrate having a first and a second surface on opposite sides of the first substrate; and
a plurality of contact arrangements disposed on the first surface of the first substrate;
wherein the plurality of contact arrangements comprises:
first contacts disposed as a ring to provide a first array of the plurality of contact arrangements on the first surface;
second contacts disposed interior to the ring of the first contacts to provide a second array of the plurality of contact arrangements on the first surface;
wherein the first contacts and the second contacts are for interconnection with first microelectronic dies and second microelectronic dies;
wherein the second microelectronic dies are disposed below the first microelectronic dies in same a package as the first microelectronic dies; and
wherein the first microelectronic dies and the second microelectronic dies include at least two ranks thereof for commonly sharing the first contacts and the second contacts among the first microelectronic dies and the second microelectronic dies.
2. The microelectronic assembly according to claim 1 , further comprising:
a second substrate having a third and a fourth surface on opposite sides of the second substrate;
wherein the first contacts and the second contacts are respectively interconnected to first stack wires and second stack wires for interconnecting to the third surface of the second substrate.
3. The microelectronic assembly according to claim 2 , wherein:
the first stack wires and the second stack wires extend from the second surface of the first substrate for interconnecting to the third surface of the second substrate;
the second surface and the third surface define an interior region therebetween for the second microelectronic dies; and
the first stack wires and the second stack wires are for interconnecting to the third surface for coupling to the first microelectronic dies disposed above the fourth surface.
4. The microelectronic assembly according to claim 2 , wherein the first contacts and the second contacts are for interconnecting to the second microelectronic dies disposed above the second surface.
5. The microelectronic assembly according to claim 3 , wherein the second contacts are control and address signal contacts for the first microelectronic dies and the second microelectronic dies.
6. The microelectronic assembly according to claim 5 , wherein the first contacts are data signal contacts for the first microelectronic dies and the second microelectronic dies.
7. The microelectronic assembly according to claim 1 , wherein the first microelectronic dies comprise:
a first memory die and a second memory die spaced apart from one another with each in a latitudinal orientation; and
a third memory die and a fourth memory die spaced apart from one another with each in a longitudinal orientation.
8. The microelectronic assembly according to claim 1 , wherein the first microelectronic dies and the second microelectronic dies are of a memory module having at least two ranks and at least one communication channel.
9. The microelectronic assembly according to claim 1 , wherein the first microelectronic dies and the second microelectronic dies are of a memory module having two ranks and one communication channel.
10. A microelectronic assembly, comprising:
a first substrate having a first and a second surface on opposite sides of the first substrate; and
a plurality of contact arrangements disposed on the first surface of the first substrate;
wherein the plurality of contact arrangements comprises:
first contacts disposed as a first block and a first L-shaped region spaced apart from one another in a first quadrant of the plurality of contact arrangements on the first surface;
second contacts disposed as a second block and a second L-shaped region spaced apart from one another in a second quadrant of the plurality of contact arrangements on the first surface;
wherein the first contacts and the second contacts are for interconnection with first microelectronic dies and second microelectronic dies;
wherein the first microelectronic dies and the second microelectronic dies are in same a package; and
wherein the first microelectronic dies and the second microelectronic dies include at least two ranks thereof for commonly sharing the first contacts and the second contacts among the first microelectronic dies and the second microelectronic dies.
11. The microelectronic assembly according to claim 10 , wherein:
the first L-shaped region and the second L-shaped region are respective corners of a quadrilateral defining a first central region having disposed therein the first block and the second block;
the first quadrant and the second quadrant are spaced apart from one another;
the first L-shaped region and the second L-shaped region are diagonally opposed to one another; and
the first block and the second block are diagonally opposed to one another.
12. The microelectronic assembly according to claim 10 , further comprising:
a second substrate having a third and a fourth surface on opposite sides of the second substrate;
wherein:
the first contacts of the first block and the first L-shaped region are respectively interconnected to a first set and a second set of stack wires;
the second contacts of the second block and the second L-shaped region are respectively interconnected to a third set and a fourth set of the stack wires;
the stack wires extend from the second surface of the first substrate for interconnecting to the third surface of the second substrate; and
the second surface and the third surface define an interior region therebetween for locating a first pair of the first microelectronic dies and a first pair of the second microelectronic dies in the interior region.
13. The microelectronic assembly according to claim 10 , wherein the stack wires are for interconnecting to a second pair of the first microelectronic dies and a second pair of the second microelectronic dies disposed above the fourth surface.
14. The microelectronic assembly according to claim 13 , wherein:
the first contacts are for interconnecting to the first pair and the second pair of the first microelectronic dies; and
the second contacts are for interconnecting to the first pair and the second pair of the second microelectronic dies.
15. The microelectronic assembly according to claim 14 , wherein the first contacts of the first block and the second contacts of the second block are control and address signal contacts respectively for the first microelectronic dies and the second microelectronic dies.
16. The microelectronic assembly according to claim 9 , wherein:
a first memory die and a second memory die are spaced apart from one another with each in a latitudinal orientation for the second pair of the first microelectronic dies; and
a third memory die and a fourth memory die are spaced apart from one another with each in a longitudinal orientation for the second pair of the second microelectronic dies.
17. The microelectronic assembly according to claim 1 , wherein the first microelectronic dies and the second microelectronic dies are of a memory module having at least two ranks and at least two communication channels.
18. A method for forming a microelectronic assembly, comprising:
obtaining a first substrate having a first surface and a second surface on opposite sides of the first substrate;
forming a plurality of contact arrangements on the first surface of the first substrate;
wherein the plurality of contact arrangements comprises:
first contacts disposed as a first block and a first L-shaped region spaced apart from one another in a first quadrant of the plurality of contact arrangements on the first surface;
second contacts disposed as a second block and a second L-shaped region spaced apart from one another in a second quadrant of the plurality of contact arrangements on the first surface;
wherein the first contacts and the second contacts are for interconnection with first microelectronic dies and second microelectronic dies;
wherein the first microelectronic dies and the second microelectronic dies are in same a package; and
wherein the first microelectronic dies and the second microelectronic dies include at least two ranks thereof for commonly sharing the first contacts and the second contacts among the first microelectronic dies and the second microelectronic dies.
19. The method according to claim 18 , further comprising:
obtaining a second substrate having a third and a fourth surface on opposite sides of the second substrate;
interconnecting the first contacts of the first block and the first L-shaped region respectively to a first set and a second set of stack wires;
interconnecting the second contacts of the second block and the second L-shaped region respectively to a third set and a fourth set of the stack wires;
wherein the stack wires extend from the second surface of the first substrate for interconnecting to the third surface of the second substrate; and
wherein the second surface and the third surface define an interior region therebetween for locating a first pair of the first microelectronic dies and a first pair of the second microelectronic dies in the interior region.
20. The method according to claim 19 , further comprising interconnecting the stack wires to a second pair of the first microelectronic dies and a second pair of the second microelectronic dies disposed above the fourth surface.