Apparatuses and systems for a bias network with accurate quiescent current control
Embodiments of apparatuses and systems for a bias network providing accurate quiescent current control are generally described herein. Other embodiments may be described and claimed.
1. A circuit comprising:
a radio frequency (RF) transistor; and
a bias network coupled with a base of the RF transistor, the bias network including:
a multi-gate depletion-mode field-effect transistor (D-FET) to provide a quiescent current, wherein the multi-gate D-FET is a triple-gate D-FET; and
a current mirror that includes a heterojunction bipolar transistor (HBT) to provide a mirrored current, wherein the quiescent current is proportional to the mirror current.
2. The circuit of claim 1 , wherein the multi-gate D-FET is a first multi-gate D-FET and the circuit further comprising:
a current source that includes a second multi-gate D-FET that is coupled in parallel with the HBT.
3. The circuit of claim 2 , wherein the current source is a shunt current source.
4. The circuit of claim 2 , wherein the current source is to at least partially compensate process variation with respect to the first multi-gate D-FET.
5. The circuit of claim 1 , wherein the bias network is to be coupled with a digital-to-analog converter (DAC) to provide a regulator voltage (Vreg) that is between approximately 0.7 volts (V) and 2.9 V.
6. The circuit of claim 5 , wherein the DAC is to provide the regulator voltage below 2.5 V.
7. The circuit of claim 1 , wherein the RF transistor is a drive stage of a power amplifier.
8. The circuit of claim 1 , wherein the RF transistor is a final stage of a power amplifier.
9. The circuit of claim 1 , further comprising a capacitor coupled with the base of the HBT and a collector of the HBT.
10. A circuit comprising:
a radio frequency (RF) transistor; and
a bias network including:
a first branch having:
a terminal to receive a battery voltage;
a multi-gate depletion mode field effect transistor (D-FET) coupled with the terminal; and
a node coupled with a base of the RF transistor; and
a second branch having:
a terminal to receive a regulator voltage;
a heterojunction bipolar transistor (HBT) having a base coupled with the node of the first branch; and
a capacitor coupled with the base of the HBT and a collector of the HBT.
11. The circuit of claim 10 , wherein the first branch further comprises a capacitor coupled with the node and ground.
12. The circuit of claim 10 , wherein the base of the HBT is coupled with the node through a resistor.
13. The circuit of claim 10 , wherein the multi-gate D-FET is a first multi-gate D-FET and the second branch further comprises a second multi-gate D-FET coupled in parallel with the HBT.
14. The circuit of claim 13 , wherein the HBT is a current mirror, and the second multi-gate D-FET is a current source.
15. The circuit of claim 14 , wherein the current source is to at least partially compensate process variation with respect to the multi-gate D-FET.
16. The circuit of claim 10 , wherein the multi-gate D-FET is a triple-gate D-FET.
17. A system comprising:
a power source to provide a battery voltage;
a transceiver to provide a transmit signal and a regulator voltage; and
a power amplifier (PA) module comprising:
a power amplifier stage coupled with the transceiver to receive and amplify the transmit signal; and
a bias network coupled with the power amplifier stage, the power source, and the transceiver, the bias network including a multi-gate depletion mode field effect transistor (D-FET) to provide a quiescent current to the power amplifier stage based on the regulator voltage, wherein the multi-gate D-FET is a triple-gate D-FET.
18. The system of claim 17 , wherein the bias network further includes a heterojunction bipolar transistor (HBT) to provide a mirror current to set the quiescent current through the power amplifier stage.
19. The system of claim 18 , wherein the bias network further includes a multi-gate (D-FET) current source coupled in parallel with the HBT to at least partially compensate process variation with respect to the multi-gate D-FET.
20. The system of claim 17 , wherein the transceiver includes a digital-to-analog converter (DAC) to provide the regulator voltage with a range of approximately 2.2 V.
21. The system of claim 17 , wherein the system is a mobile computing device.
22. The system of claim 18 , further comprising a capacitor coupled with the base of the HBT and a collector of the HBT.