Semiconductor storage device
A semiconductor includes a plurality of memory cell arrays each of which includes a plurality of memory cells. Bitlines extend in one direction in the memory cell arrays to transfer data stored in the memory cells. Wordlines extend perpendicular to the bitlines in the memory cell arrays to select at least one of the memory cells. Local data lines extend parallel to the wordlines outside of the memory cell arrays and convey signals from bitlines. Global data lines convey signals from the local data lines. The global data lines include a part extending parallel to the wordlines and the part is disposed over another one of the memory cell arrays other than a selected memory cell array.
1. A semiconductor device comprising:
a plurality of memory cell arrays each of which includes a plurality of memory cells;
bitlines extending in a first direction in the memory cell arrays to transfer data stored in the memory cells;
wordlines extending in a second direction substantially perpendicular to the first direction in the memory cell arrays to select at least one of the memory cells of one or more selected memory cell arrays of the plurality of memory cell arrays;
local data lines which extend parallel to the wordlines outside of the memory cell arrays and which convey signals from the bitlines, the signals conveyed from the bitlines representing data transferred from the at least one memory cells of the one or more selected memory cell arrays; and
global data lines configured to convey signals from the local data lines;
wherein the global data lines include at least one global data line having a part extending parallel to the wordlines and the part is disposed over a memory cell array that is not a selected memory cell array, wherein the at least one global data line has another part that is arranged between two adjacent memory cell arrays of the plurality of memory cell arrays, the other part being substantially perpendicular to the part extending parallel to the wordlines.
2. The semiconductor device as claimed in claim 1 , wherein the part extending parallel to the wordlines is coupled to a main amplifier outside of the memory cell arrays.
3. The semiconductor device as claimed in claim 2 , further comprising a main amplifier enable line configured to convey a signal activating the main amplifier, wherein the main amplifier enable line extends alongside of a corresponding local data line of the local data lines and a corresponding global data line of the global data lines.
4. The semiconductor device as claimed in claim 2 , further comprising a main amplifier enable line configured to convey a signal activating the main amplifier, wherein the main amplifier enable line is disposed over the non-selected memory cell array.
5. The semiconductor device as claimed in claim 1 , wherein the other part of the at least one global data line is between the local data lines and the part extending parallel to the wordlines.
6. A semiconductor device comprising:
a memory cell array including a plurality of memory cells;
bitlines extending in one direction in the memory cell array to transfer data stored in the memory cells;
wordlines extending perpendicular to the bitlines in the memory cell array to select at least one of the memory cells;
local data lines which extend parallel to the wordlines outside of the memory cell array and which convey signals from bitlines;
global data lines which convey signals from the local data lines;
wherein the global data lines includes a first global data line, the first global data line having a first part arranged between the memory cell array and an adjacent memory cell array and a second part extending parallel to the wordlines and being perpendicular to the first part, and the second part is disposed over the memory cell array.
7. The semiconductor device as claimed in claim 6 , wherein the second part couples to a main amplifier outside of the memory cell arrays.
8. The semiconductor device as claimed in claim 7 , further comprising a main amplifier enable line configured to convey a signal activating the main amplifier, wherein the main amplifier enable line extends alongside of a corresponding local data line of the local data lines and a corresponding global data line of the global data lines.
9. The semiconductor device as claimed in claim 7 , further comprising a main amplifier enable line configured to convey a signal activating the main amplifier, wherein the main amplifier enable line is disposed over the memory cell array.
10. The semiconductor device as claimed in claim 6 , wherein the first part of the first global data line extends between the second part and the local data lines.
11. The semiconductor device as claimed in claim 1 , wherein the non-selected memory cell array is located at a different position along the first direction than any of the one or more selected memory cell arrays.
12. The semiconductor device as claimed in claim 1 , wherein the two adjacent memory cell arrays are selected memory cell arrays.
13. The semiconductor device as claimed in claim 12 , wherein the two adjacent memory cell arrays are selected simultaneously.
14. The semiconductor device as claimed in claim 1 , wherein each local data line does not extend along multiple memory cell arrays located at different positions in the second direction.
15. The semiconductor device as claimed in claim 6 , wherein the adjacent memory cell array is adjacent to the memory cell array along the wordline direction.